Abstract: A slave-type interface circuit which can receive signals from a bus if the coding A.sub.0, A.sub.1 and A.sub.2 of its inputs S.sub.0, S.sub.1 and S.sub.2 corresponds to that mode of operation. The signals from the bus are then delivered to the inputs L.sub.1 and L.sub.2. With another mode of operation the coding of inputs S.sub.0, S.sub.1 and S.sub.2 corresponds to off-line operation on the basis of logic levels applied to the same inputs L.sub.1 and L.sub.2. A branching block (SBL) directs the signals from the inputs L.sub.1 and L.sub.2 either to a bus receiver RBUS or directly to a decoder CDEC controlling a group of switches (COM). In the case of operation with a bus, the bus receiver (RBUS) controls the logic for the progress for operations.

Abstract: A slave-type interface circuit operating with a series bus in a configuration in which writing takes place after recognition of an address. A cycle transmitted by the bus contains an address sequence and a data sequence.The circuit controls a plurality of user circuits (COM) on the basis of data stored in a memory (M) and of a decoder (CDEC).A register (REG) and a bus logic (BUSL) receive at their inputs (L.sub.1, L.sub.2) information (SDA) and clock (SCL) signals. The bus logic (BUSL) receives from an identification circuit (AIC) a signal (DVA) indicating whether or not the address transmitted by the bus corresponds to an address A.sub.0, A.sub.1, A.sub.2 displayed at the inputs S.sub.0, S.sub.1 and S.sub.2. It controls the circuit on the basis of the register (REG) initialization signal (RST1), a signal LDS) for the authorization of the loading of data into the memory (M) and an acceptance signal (ACK) transmitted in the direction of the bus.