Patents by Inventor Leonid Baraz

Leonid Baraz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230403259
    Abstract: According to an aspect, a method includes generating a computer event by a computing device of a management system, where the computer event includes information about a computer action initiated by activity on the computing device or information about a performance of the computing device. The method includes generating sequencing information for the computer event, encrypting the computer event, storing the encrypted computer event in a storage device of the computing device, and transmitting, over a network, an event request to a server, where the event request includes the encrypted computer event and the sequencing information.
    Type: Application
    Filed: June 8, 2022
    Publication date: December 14, 2023
    Inventors: Leonid Baraz, Tracie Chan, Zach Trudo, Brian Robert Malcolm, Yaohong Xi, Mattias Nissler, Jason Chun-Hong Wong, Stephen John Konig
  • Patent number: 7076769
    Abstract: A method and apparatus for reproduction of a legacy ISA application corresponding to a target ISA application state at an execution stop point are described. In one embodiment, the method includes the translation of a binary application generated for a legacy instruction set architecture (ISA) into a translated binary application for a target ISA. During translation, one or more instructions within the translated binary application are selected as commit point instructions. Once selected, the translated binary application is modified to store a source ISA application state corresponding to a target ISA application state prior to each selected commit point. In addition, the selected commit points indicate the location of the stored source ISA application state information.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: July 11, 2006
    Assignee: Intel Corporation
    Inventor: Leonid Baraz
  • Publication number: 20040194070
    Abstract: A method and apparatus for reproduction of a legacy ISA application corresponding to a target ISA application state at an execution stop point are described. In one embodiment, the method includes the translation of a binary application generated for a legacy instruction set architecture (ISA) into a translated binary application for a target ISA. During translation, one or more instructions within the translated binary application are selected as commit point instructions. Once selected, the translated binary application is modified to store a source ISA application state corresponding to a target ISA application state prior to each selected commit point. In addition, the selected commit points indicate the location of the stored source ISA application state information.
    Type: Application
    Filed: March 28, 2003
    Publication date: September 30, 2004
    Inventor: Leonid Baraz
  • Publication number: 20030217356
    Abstract: One or more instructions of a program are analyzed. The program is modified to expand a register set for a routine in the program.
    Type: Application
    Filed: January 10, 2002
    Publication date: November 20, 2003
    Inventors: Leonid Baraz, Tevi Devor
  • Patent number: 6360316
    Abstract: A method for detecting independent predicated instructions comprises associating all instructions within a block of code with true and false bit vectors that have bit locations corresponding to instructions that produce pairs of mutually exclusive predicates. A computation is performed in which the true bit vectors associated with the first and second instructions are EXCLUSIVE-ORed to produce a first result. The false bit vectors associated with the first and second instructions are EXCLUSIVE-ORed to produce a second result. The first and second results are then ANDed to produce a third result. If the third result is a non-zero result, the first and second instructions are independent.
    Type: Grant
    Filed: June 16, 1999
    Date of Patent: March 19, 2002
    Assignee: Intel Corporation
    Inventor: Leonid Baraz
  • Patent number: 5903760
    Abstract: A method for increasing the performance of binary translated conditional instructions. According to one embodiment of the invention, a conditional instruction compatible with the first ISA is decoded. The condition of the conditional instruction is dependent on at least on status flag. The conditional instruction is translated to be compatible with a second ISA, wherein the condition of the conditional instruction is altered to be dependent on a previously computed difference between two values, the difference residing in a memory location.
    Type: Grant
    Filed: June 27, 1996
    Date of Patent: May 11, 1999
    Assignee: Intel Corporation
    Inventors: Yaron Farber, Yossi Levhari, Leonid Baraz, Gallia Ladiray
  • Patent number: 5721927
    Abstract: A method for enabling a first block of instructions to verify whether the first block of instructions follows a second block of instructions in an order of execution. The method includes appending a compare instruction to the first block of instructions. The compare instruction compares a first value from the first block of instructions with a second value from the second block of instructions, which precedes the first block of instructions in the order of execution. The method further includes appending a branching instruction to the first block of instructions. The branching instruction is executed in response to the first value being unequal to the second value. The branching instruction, when executed, branches to an alternative look-up routine to obtain a block of instructions that follows the second block of instructions in the order of execution.
    Type: Grant
    Filed: August 7, 1996
    Date of Patent: February 24, 1998
    Assignee: Intel Corporation
    Inventors: Leonid Baraz, Yaron Farber