Abstract: There is provided a method, apparatus and integrated circuit for measuring a signal, the apparatus comprising a plurality of sample stages arranged in series, each sample stage comprising a delay element, and a sample element, wherein an input of the sample element is coupled to an output of the delay element, and a strobe line for controlling a sample time of the sample elements, the strobe line comprising a plurality of strobe delay elements arranged in series, wherein an output of each strobe delay element is coupled to one or more sample elements.

Abstract: A register file module comprising at least one register array comprising a plurality of latch devices is described. The plurality of latch devices is arranged to individually provide memory bit-cells when the register file module is configured to operate in a first, functional operating mode, and at least one clock control component is arranged to receive a clock signal and to propagate the clock signal to the latch devices within the at least one register array. The register file module is configurable to operate in a second, scan mode in which the latch devices within the at least one register array are arranged into at least one scan chain. The at least one clock control component is arranged to propagate the clock signal to the latch devices within the at least one register array such that alternate latch devices within the at least one scan chain receive an inverted form of the clock signal.

Abstract: An electronic device may include a set of two or more scan chains and a buffer chain. Each of the scan chains includes a sequence of stateful elements connected in series, and each of the scan chains is arranged to hold a string having a length identical to the length of the respective scan chain. The strings of the scan chains are shifted in parallel from the scan chains into the memory unit and back from the memory unit into the respective scan chains. The store operation and the restore operation each include at least N0 elementary downstream shift operations. The set of scan chains includes a short chain and a detour chain, and the short chain has a length N1 which is shorter than N0. The set of scan chains further includes a buffer chain. The output end of the short chain is coupled to an input end of the buffer chain. The buffer chain is provided at least partly by the detour chain.

Abstract: A method of detecting irregular high current flow within an integrated circuit (IC) device is described. The method comprises obtaining infrared (IR) emission information for the IC device, identifying at least one functional component within the IC device comprising a high current flow, based at least partly on the obtained IR emission information, obtaining IR emission information for at least one reference component within the IC device, and determining whether the high current flow of the at least one functional component comprises an irregular high current flow based at least partly on a comparison of respective IR emission information for the at least one functional component and the at least one reference component.

Abstract: A system for on-die voltage difference measurement on a pass device comprises a first voltage controlled oscillator circuit having a first voltage control input connectable to a first terminal of the pass device; a second voltage controlled oscillator circuit having a second voltage control input connectable to a second terminal of the pass device; a first counter circuit arranged to count oscillation periods of a first output signal from the first voltage controlled oscillator circuit and to provide a stop signal when a predefined number of the oscillation periods of the first output signal is counted; and a second counter circuit arranged to count oscillation periods of a second output signal from the second voltage controlled oscillator circuit and to stop counting depending on the stop signal.

Abstract: A bypass capacitor circuit for an integrated circuit (IC) comprises one or more capacitive devices, each arranged in a segment of a seal ring area of a die, which comprises the IC. A method of providing a bypass capacitance for an IC comprises providing a semiconductor wafer device comprising a plurality of dies, each comprising an IC; arranging one or more capacitive devices in a seal ring area of at least one of the IC; dicing the semiconductor wafer device; in a test mode, for each of the one or more capacitive devices, enabling the capacitive device, determining an operability parameter value indicative of an operability of the capacitive device, and storing the operability parameter in a memory device; and in a normal operation mode, providing a bypass capacitance to the IC depending on a capacitance of one or more of the capacitive devices having an associated operability parameter value indicative of a non-defectiveness of the corresponding capacitive device.

Abstract: An electronic device includes a set of two or more scan chains and a buffer chain. Each of the scan chains includes a sequence of stateful elements connected in series, and each of the scan chains is arranged to hold a string having a length identical to the length of the (50) respective scan chain. The strings of the scan chains are shifted in parallel from the scan chains into the memory unit and back from the memory unit into the respective scan chains. The store operation and the restore operation each include at least N0 elementary downstream shift operations. The set (100) of scan chains includes a short chain and a detour chain, wherein the short chain (C1) has a length N1 shorter than N0, and the buffer chain. The output end of the short chain is coupled to an input end of the (150) buffer chain. The buffer chain is provided at least partly by the detour chain.

Abstract: There is provided a method, apparatus and integrated circuit for measuring a signal, the apparatus comprising a plurality of sample stages arranged in series, each sample stage comprising a delay element, and a sample element, wherein an input of the sample element is coupled to an output of the delay element, and a strobe line for controlling a sample time of the sample elements, the strobe line comprising a plurality of strobe delay elements arranged in series, wherein an output of each strobe delay element is coupled to one or more sample elements.

Abstract: A clock distribution module for a digital synchronous system is described. The clock distribution module comprising a first node arranged to comprise a clock signal comprising a propagation delay relative to a reference clock signal, at least one further node arranged to comprise a clock signal comprising a propagation delay relative to the reference clock signal corresponding to that of the first node, and a clock configuration module. The clock configuration module is arranged to receive at least one indication of clock skew between the first node and at least one further node of the clock distribution module, and to selectively couple the first node to the at least one further node based at least partly on the at least one indication of clock skew there between.

Abstract: A sequential logic circuit comprising a first latch component comprising a data input arranged to receive an input signal, a data output arranged to output a current logical state of the first latch component and a clock input arranged to receive a clock signal; the first latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a first logical state, and to comprise a latched state upon the clock signal received thereby comprising a second logical state, and a second latch component comprising a data input arranged to receive an input signal, a data output operably coupled to an output of the sequential logic circuit and arranged to output a current state of the second latch component and a clock input arranged to receive a clock signal; the second latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a second logical state, and to comprise a latched state upon the clock signal received thereby c

Abstract: A method for compensating a timing signal with which an outputting of data states of at least one data signal is synchronised. The method comprises receiving a current set of data states and a next set of data states, identifying state transitions between the current set of data states and the next set of data states determining an amount of compensation to apply to the timing signal based at least partly on the state transitions identified between the current set of data states and the next set of data states, and applying the determined amount of compensation to the timing signal such that the compensation applies to the outputting of the next set of data states.

Abstract: A register file module comprising at least one register array comprising a plurality of latch devices is described. The plurality of latch devices is arranged to individually provide memory bit-cells when the register file module is configured to operate in a first, functional operating mode, and at least one clock control component is arranged to receive a clock signal and to propagate the clock signal to the latch devices within the at least one register array. The register file module is configurable to operate in a second, scan mode in which the latch devices within the at least one register array are arranged into at least one scan chain. The at least one clock control component is arranged to propagate the clock signal to the latch devices within the at least one register array such that alternate latch devices within the at least one scan chain receive an inverted form of the clock signal.

Abstract: A system for on-die voltage difference measurement on a pass device comprises a first voltage controlled oscillator circuit having a first voltage control input connectable to a first terminal of the pass device; a second voltage controlled oscillator circuit having a second voltage control input connectable to a second terminal of the pass device; a first counter circuit arranged to count oscillation periods of a first output signal from the first voltage controlled oscillator circuit and to provide a stop signal when a predefined number of the oscillation periods of the first output signal is counted; and a second counter circuit arranged to count oscillation periods of a second output signal from the second voltage controlled oscillator circuit and to stop counting depending on the stop signal.

Abstract: An integrated circuit device comprising at least one voltage supply module arranged to receive at an input thereof at least one control signal and to provide at an output thereof a voltage signal in accordance with the received at least one control signal, and at least one control module comprising at least one feedback loop between the output of the at least one voltage supply module and the input of the at least one voltage supply module, and arranged to generate the at least one control signal based at least partly on the voltage level of the voltage signal output by the at least one voltage supply module. The at least one control module is further arranged to receive at an input thereof at least one instantaneous indication of a load current at the output of the at least one voltage supply module, and apply a compensation to the at least one control signal provided to the at least one voltage supply module based at least partly on the received at least one indication of the load current.

Abstract: A clock distribution module for a digital synchronous system is described. The clock distribution module comprising a first node arranged to comprise a clock signal comprising a propagation delay relative to a reference clock signal, at least one further node arranged to comprise a clock signal comprising a propagation delay relative to the reference clock signal corresponding to that of the first node, and a clock configuration module. The clock configuration module is arranged to receive at least one indication of clock skew between the first node and at least one further node of the clock distribution module, and to selectively couple the first node to the at least one further node based at least partly on the at least one indication of clock skew there between.

Abstract: A sequential logic circuit comprising a first latch component comprising a data input arranged to receive an input signal, a data output arranged to output a current logical state of the first latch component and a clock input arranged to receive a clock signal; the first latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a first logical state, and to comprise a latched state upon the clock signal received thereby comprising a second logical state, and a second latch component comprising a data input arranged to receive an input signal, a data output operably coupled to an output of the sequential logic circuit and arranged to output a current state of the second latch component and a clock input arranged to receive a clock signal; the second latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a second logical state, and to comprise a latched state upon the clock signal received thereby c

Abstract: A method of detecting irregular high current flow within an integrated circuit (IC) device is described. The method comprises obtaining infrared (IR) emission information for the IC device, identifying at least one functional component within the IC device comprising a high current flow, based at least partly on the obtained IR emission information, obtaining IR emission information for at least one reference component within the IC device, and determining whether the high current flow of the at least one functional component comprises an irregular high current flow based at least partly on a comparison of respective IR emission information for the at least one functional component and the at least one reference component.

Abstract: An integrated circuit includes a plurality of power gating elements for controlling power applied to a first module which is in a powered off state, while a second module is in a powered on state, the second module being coupled to receive at least one signal from the first module when the first module is powered on. A a synchronization controller is provided for controlling the power gating elements to ramp up the power gated to the first module in order to power it up and, for a time while the power gated to the first module is below a first level, reducing the power gated to the second module, and for a time when the power gated to the first module is above the first level, increasing the power gated to the second module.

Abstract: An integrated circuit device comprising at least one voltage supply module arranged to receive at an input thereof at least one control signal and to provide at an output thereof a voltage signal in accordance with the received at least one control signal, and at least one control module comprising at least one feedback loop between the output of the at least one voltage supply module and the input of the at least one voltage supply module, and arranged to generate the at least one control signal based at least partly on the voltage level of the voltage signal output by the at least one voltage supply module. The at least one control module is further arranged to receive at an input thereof at least one instantaneous indication of a load current at the output of the at least one voltage supply module, and apply a compensation to the at least one control signal provided to the at least one voltage supply module based at least partly on the received at least one indication of the load current.

Abstract: There is provided a semiconductor Integrated Circuit device having forward well biasing, in which at least one protection device is connected between a supply voltage and a forward well bias voltage.