Patents by Inventor Leonid Fursin

Leonid Fursin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11710662
    Abstract: Multiple wide bandgap semiconductor wafers, each having active circuitry and an epitaxially formed backside drain contact layer, may be constructed from a single bulk semiconductor substrate by: forming foundational layers on the top of the bulk substrate via epitaxy; forming active circuitry atop the foundational layers; laser treating the backside of the bulk substrate to create a cleave line in one of the foundational layers; and exfoliating a semiconductor wafer from the bulk substrate, where the exfoliated semiconductor wafer contains the active circuits and at least a portion of the foundational layers. Wafers containing the foundational layers without complete active devices may be produced in a similar manner. The foundational layers may comprise a drain contact layer and a drift layer, and may additionally include a buffer layer between the drain contact layer and the drift layer.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: July 25, 2023
    Assignee: United Silicon Carbide, Inc.
    Inventors: Anup Bhalla, Leonid Fursin
  • Publication number: 20210005517
    Abstract: Multiple wide bandgap semiconductor wafers, each having active circuitry and an epitaxially formed backside drain contact layer, may be constructed from a single bulk semiconductor substrate by: forming foundational layers on the top of the bulk substrate via epitaxy; forming active circuitry atop the foundational layers; laser treating the backside of the bulk substrate to create a cleave line in one of the foundational layers; and exfoliating a semiconductor wafer from the bulk substrate, where the exfoliated semiconductor wafer contains the active circuits and at least a portion of the foundational layers. Wafers containing the foundational layers without complete active devices may be produced in a similar manner. The foundational layers may comprise a drain contact layer and a drift layer, and may additionally include a buffer layer between the drain contact layer and the drift layer.
    Type: Application
    Filed: September 23, 2020
    Publication date: January 7, 2021
    Inventors: Anup Bhalla, Leonid Fursin
  • Patent number: 10825733
    Abstract: Multiple wide bandgap semiconductor wafers, each having active circuitry and an epitaxially formed backside drain contact layer, may be constructed from a single bulk semiconductor substrate by: forming foundational layers on the top of the bulk substrate via epitaxy; forming active circuitry atop the foundational layers; laser treating the backside of the bulk substrate to create a cleave line in one of the foundational layers; and exfoliating a semiconductor wafer from the bulk substrate, where the exfoliated semiconductor wafer contains the active circuits and at least a portion of the foundational layers. Wafers containing the foundational layers without complete active devices may be produced in a similar manner. The foundational layers may comprise a drain contact layer and a drift layer, and may additionally include a buffer layer between the drain contact layer and the drift layer.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: November 3, 2020
    Assignee: United Silicon Carbide, Inc.
    Inventors: Anup Bhalla, Leonid Fursin
  • Publication number: 20200135565
    Abstract: Multiple wide bandgap semiconductor wafers, each having active circuitry and an epitaxially formed backside drain contact layer, may be constructed from a single bulk semiconductor substrate by: forming foundational layers on the top of the bulk substrate via epitaxy; forming active circuitry atop the foundational layers; laser treating the backside of the bulk substrate to create a cleave line in one of the foundational layers; and exfoliating a semiconductor wafer from the bulk substrate, where the exfoliated semiconductor wafer contains the active circuits and at least a portion of the foundational layers. Wafers containing the foundational layers without complete active devices may be produced in a similar manner. The foundational layers may comprise a drain contact layer and a drift layer, and may additionally include a buffer layer between the drain contact layer and the drift layer.
    Type: Application
    Filed: October 25, 2018
    Publication date: April 30, 2020
    Inventors: Anup Bhalla, Leonid Fursin
  • Patent number: 9917180
    Abstract: The present invention concerns a monolithically merged trenched-and-implanted Bipolar Junction Transistor (TI-BJT) with antiparallel diode and a method of manufacturing the same. Trenches are made in a collector, base, emitter stack downto the collector. The base electrode is formed on an implanted base contact region at the bottom surface of the trench. The present invention also provides for products produced by the methods of the present invention and for apparatuses used to perform the methods of the present invention.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: March 13, 2018
    Assignee: United Silicon Carbide, Inc.
    Inventors: Anup Bhalla, Leonid Fursin
  • Patent number: 9721944
    Abstract: A hybrid semiconductor bipolar switch in which a normally-on high-voltage wide-bandgap semiconductor bipolar switch and a normally-off field effect transistor are connected in a cascode (Baliga-pair) configuration. The switch may be constructed as a stacked hybrid device where a discrete transistor is bonded on top of a bipolar switch. Power systems may use plural switches paired with anti-parallel diodes.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: August 1, 2017
    Assignee: United Silicon Carbide, Inc.
    Inventors: Leonid Fursin, Anup Bhalla
  • Publication number: 20170213908
    Abstract: Disclosed herein is a shielded-gate silicon carbide trench MOS-controlled switch, such as a MOSFET or IGBT, with a reduced Miller capacitance. The switch disclosed herein can be used in a variety of applications, including high temperature and/or high voltage power conversion.
    Type: Application
    Filed: July 1, 2015
    Publication date: July 27, 2017
    Inventors: Leonid FURSIN, Anup BHALLA
  • Publication number: 20170005183
    Abstract: The present invention concerns a monolithically merged trenched-and-implanted Bipolar Junction Transistor (TI-BJT) with antiparallel diode and a method of manufacturing the same. Trenches are made in a collector, base, emitter stack downto the collector. The base electrode is formed on an implanted base contact region at the bottom surface of the trench. The present invention also provides for products produced by the methods of the present invention and for apparatuses used to perform the methods of the present invention.
    Type: Application
    Filed: February 10, 2015
    Publication date: January 5, 2017
    Applicant: United Silicon Carbide, Inc.
    Inventors: Anup BHALLA, Leonid FURSIN
  • Patent number: 9331068
    Abstract: A hybrid semiconductor bipolar switch in which a normally-on high-voltage wide-bandgap semiconductor bipolar switch and a normally-off field effect transistor are connected in a cascode (Baliga-pair) configuration. The switch may be constructed as a stacked hybrid device where a discrete transistor is bonded on top of a bipolar switch. Power systems may use plural switches paired with anti-parallel diodes.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: May 3, 2016
    Assignee: United Silicon Carbide, Inc.
    Inventors: Leonid Fursin, Anup Bhalla
  • Publication number: 20160118381
    Abstract: A hybrid semiconductor bipolar switch in which a normally-on high-voltage wide-bandgap semiconductor bipolar switch and a normally-off field effect transistor are connected in a cascode (Baliga-pair) configuration. The switch may be constructed as a stacked hybrid device where a discrete transistor is bonded on top of a bipolar switch. Power systems may use plural switches paired with anti-parallel diodes.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 28, 2016
    Inventors: Leonid Fursin, Anup Bhalla
  • Patent number: 9324807
    Abstract: A monolithically integrated MOS channel in gate-source shorted mode is used as a diode for the third quadrant conduction path for a power MOSFET. The MOS diode and MOSFET can be constructed in a variety of configurations including split-cell and trench. The devices may be formed of silicon carbide, gallium nitride, aluminum nitride, aluminum gallium nitride, diamond, or similar semiconductor. Low storage capacitance and low knee voltage for the MOS diode can be achieved by a variety of means. The MOS diode may be implemented with channel mobility enhancement materials, and/or have a very thin/high permittivity gate dielectric. The MOSFET gate conductor and MOS diode gate conductor may be made of polysilicon doped with opposite dopant types. The surface of the MOS diode dielectric may be implanted with cesium.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: April 26, 2016
    Assignee: United Silicon Carbide, Inc.
    Inventors: Anup Bhalla, Leonid Fursin
  • Patent number: 9054183
    Abstract: The present invention provides AccuFETs with single or dual accumulation channels and methods for manufacturing the same. The present invention also provides for products produced by the methods of the present invention and for apparatuses used to perform the methods of the present invention.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: June 9, 2015
    Assignee: United Silicon Carbide, Inc.
    Inventors: Leonid Fursin, Xueqing Li
  • Publication number: 20150115289
    Abstract: A hybrid semiconductor bipolar switch in which a normally-on high-voltage wide-bandgap semiconductor bipolar switch and a normally-off field effect transistor are connected in a cascode (Baliga-pair) configuration. The switch may be constructed as a stacked hybrid device where a discrete transistor is bonded on top of a bipolar switch. Power systems may use plural switches paired with anti-parallel diodes.
    Type: Application
    Filed: October 30, 2014
    Publication date: April 30, 2015
    Inventors: Leonid Fursin, Anup Bhalla
  • Publication number: 20140015036
    Abstract: The present invention provides AccuFETs with single or dual accumulation channels and methods for manufacturing the same. The present invention also provides for products produced by the methods of the present invention and for apparatuses used to perform the methods of the present invention.
    Type: Application
    Filed: July 12, 2013
    Publication date: January 16, 2014
    Applicant: UNITED SILICON CARBIDE, INC.
    Inventors: Leonid Fursin, Xueqing Li