Abstract: Methods and system for one-line synchronous interface are described. A timing device including a first buffer can be connected to a line card including a second buffer. The timing device can control the first buffer to output a synchronization pulse to the line card periodically at a time interval. For each output of the synchronization pulse, the timing device can switch the first buffer from a first output mode to a first input mode. Under the first input mode, the timing device listen for incoming data on the trace. The line card can receive the synchronization pulse periodically at the time interval. For each receipt of the synchronization pulse, the line card can switch the second buffer from a second input mode to a second output mode. Under the second output mode, the line card can transmit outgoing data on the trace.

Abstract: Systems and methods for reducing phase delay variation impact are described. A microcontroller can receive a sequence of phase offsets determined by a slave device over time. The microcontroller can determine a weight vector based on a metric associated with the sequence of phase offsets. The microcontroller can adjust a set of filter coefficients based on the weight vector. The set of filter coefficients can be filter coefficients of a filter being implemented by the slave device to filter incoming packet data.

Abstract: Systems and methods for reducing phase delay variation impact are described. A microcontroller can receive a sequence of phase offsets determined by a slave device over time. The microcontroller can determine a weight vector based on a metric associated with the sequence of phase offsets. The microcontroller can adjust a set of filter coefficients based on the weight vector. The set of filter coefficients can be filter coefficients of a filter being implemented by the slave device to filter incoming packet data.

Abstract: A method of distributing clock signals includes receiving a plurality of clock signals into a corresponding plurality of processing blocks; determining frequency offset data between a first clock signal of the plurality of clock signals and each of the other clock signals of the plurality of clock signals; periodically determining phase offset data between the first clock signal and the other clock signals; and transmitting the first clock signal, the frequency offset data, and the phase offset data on a pulse-width modulated clock signal. The method includes receiving a modulated clock signal, the modulated clock signal include a carrier clock signal, a frequency offset data, and a phase offset data on a pulse-width modulated clock signal; and recovering a plurality of clock signals based on the first clock signal, the frequency offset data, and the phase offset data.

Abstract: A system that switches between a clock signal from a first line card and a clock signal from a second line card based on information transmitted from the first line card and the second line card on timing signals is presented. Some methods include receiving a first pulse-width modulated clock signal from a first line card, the first pulse-width modulated clock signal including information regarding the status of the first line card; receiving a second pulse-width modulated clock signal from a second line card, the second pulse-width modulated clock signal including information regarding the status of the second line card; producing a clock signal from the first pulse-width modulated clock signal; and switching to producing the clock signal from the second pulse-width modulated clock signal based on the information in the first pulse-width modulated clock signal.

Abstract: In accordance with some embodiments of the present invention, a method of minimizing timing error in a precise timing protocol system includes receiving an input 1PPS signal and a clock signal; outputting an output 1PPS signal a number of clock edges after receipt of the input 1PPS signal; adjusting the clock signal until the output 1PPS signal as jumped a clock cycle; and adjusting an offset to bring the output 1PPS signal to within a half clock period. In some embodiments, further adjustments can be made to the timestamp.

Abstract: A system that switches between a clock signal from a first line card and a clock signal from a second line card based on information transmitted from the first line card and the second line card on timing signals is presented. Some methods include receiving a first pulse-width modulated clock signal from a first line card, the first pulse-width modulated clock signal including information regarding the status of the first line card; receiving a second pulse-width modulated clock signal from a second line card, the second pulse-width modulated clock signal including information regarding the status of the second line card; producing a clock signal from the first pulse-width modulated clock signal; and switching to producing the clock signal from the second pulse-width modulated clock signal based on the information in the first pulse-width modulated clock signal.

Abstract: A method of distributing clock signals includes receiving a plurality of clock signals into a corresponding plurality of processing blocks; determining frequency offset data between a first clock signal of the plurality of clock signals and each of the other clock signals of the plurality of clock signals; periodically determining phase offset data between the first clock signal and the other clock signals; and transmitting the first clock signal, the frequency offset data, and the phase offset data on a pulse-width modulated clock signal. The method includes receiving a modulated clock signal, the modulated clock signal include a carrier clock signal, a frequency offset data, and a phase offset data on a pulse-width modulated clock signal; and recovering a plurality of clock signals based on the first clock signal, the frequency offset data, and the phase offset data.

Abstract: In accordance with some embodiments of the present invention, a method of minimizing timing error in a precise timing protocol system includes receiving an input 1PPS signal and a clock signal; outputting an output 1PPS signal a number of clock edges after receipt of the input 1PPS signal; adjusting the clock signal until the output 1PPS signal as jumped a clock cycle; and adjusting an offset to bring the output 1PPS signal to within a half clock period. In some embodiments, further adjustments can be made to the timestamp.

Abstract: In one embodiment, a method comprises a wireless detector in a lighting element detecting a movable object within a prescribed detection zone of the wireless detector; and the lighting element sending a message identifying detection of the movable object to a remote gateway, allowing the remote gateway to locate the movable object.

Abstract: In one embodiment, a method comprises a wireless detector in a lighting element detecting a movable object within a prescribed detection zone of the wireless detector; and the lighting element sending a message identifying detection of the movable object to a remote gateway, allowing the remote gateway to locate the movable object.

Abstract: Methods and apparatus are disclosed for using gap packets to create a bandwidth buffer over which packets can be sent to reduce or eliminate overflow conditions. One implementation sends a series of packets from a first device to a second device, the series of packets including interspersed information packets and gap packets. The first device determines when to insert the gap packets into the series of packets, and the gap packets received by the second device are dropped. The determination of when to insert one of the gap packets into the series of packets may be based on an occupancy level of a buffer, such as, but not limited to comparing it to a predetermined or variable threshold value. Also, the rate of sending gap packets and/or the size of the gap packets may be varied to adjust the size of bandwidth buffer created by the gap packets.

Abstract: A system and method to provide redundant power to a failing line in a communication device within a communication network supporting the transmission and reception of data. Through the use of a common Y-Cable connector, a power switch is provided to provide power between an active line and a standby line to maintain a high impedance state should one line fail.

Abstract: Methods and apparatus are disclosed for identifying the relevancy of packets. In one embodiment, source addresses are associated with network topology indications. When a packet is received, its network topology indication is compared with the corresponding one retrieved from a data structure to determine whether to drop the packet. Source addresses may also be associated with authorized interfaces to determine whether a packet was received on an authorized interface. In one embodiment, a maintained network topology indication is associated with a packet. After it is processed, the corresponding latest network topology indication is retrieved and compared with that previously associated with the packet. In one embodiment, upon a change in a network topology indication associated with an interface, control packets are placed in each of the queues corresponding to the destination interface, so it can be readily identified when this update has been propagated through the system.

Abstract: A system and method to provide redundant power to a failing line in a communication device within a communication network supporting the transmission and reception of data. Through the use of a common Y-Cable connector, a power switch is provided to provide power between an active line and a standby line to maintain a high impedance state should one line fail.

Abstract: A configurable interconnect for use with high-speed electronic system components. The interconnect uses a lightweight protocol with control characters embedded into the data stream. The control characters define events such as end of packet, end of packet with error, transmit on, transmit off, synchronizing codes, and pass-through status. In one described embodiment, the protocol is used in an internetworking device node in which a pair of high-speed counter rotating rings transport data packets. The high-speed interconnect permits data packets to pass through the node without the delays which might otherwise be experienced with time division multiplex bus structures and the like.

Abstract: A configurable interconnect for use with high-speed electronic system components. The interconnect uses a lightweight protocol with control characters embedded into the data stream. The control characters define events such as end of packet, end of packet with error, transmit on, transmit off, synchronizing codes, and pass-through status. In one described embodiment, the protocol is used in an internetworking device node in which a pair of high-speed counter rotating rings transport data packets. The high-speed interconnect permits data packets to pass through the node without the delays which might otherwise be experienced with time division multiplex bus structures and the like.