Abstract: A representative integrated circuit comprises a clock signal generator that generates a clock signal, a code pattern generator that generates digital pattern data based on the clock signal, and multiple traversal local oscillator synthesizers that are coupled in a cascaded configuration. Each traversal local oscillator synthesizer includes a transversal digital-to-analog conversion (T-DAC) unit that includes a plurality of registers and a unary modulator (Umod) array. The T-DAC provides frequency selection ranges covering wide operational bands based on the digital pattern data and the clock signal.

Abstract: A representative integrated circuit comprises a clock signal generator that generates a clock signal, a code pattern generator that generates digital pattern data based on the clock signal, and a transversal digital-to-analog conversion (T-DAC) unit that includes a plurality of registers and a unary modulator (Umod) array. The T-DAC unit provides frequency selection ranges covering wide operational bands based on the digital pattern data and the clock signal.

Abstract: A representative integrated circuit comprises a clock signal generator that generates a clock signal, a code pattern generator that generates digital pattern data based on the clock signal, and multiple traversal local oscillator synthesizers that are coupled in a cascaded configuration. Each traversal local oscillator synthesizer includes a transversal digital-to-analog conversion (T-DAC) unit that includes a plurality of registers and a unary modulator (Umod) array. The T-DAC provides frequency selection ranges covering wide operational bands based on the digital pattern data and the clock signal.

Abstract: A representative integrated circuit comprises a clock signal generator that generates a clock signal, a code pattern generator that generates digital pattern data based on the clock signal, and a transversal digital-to-analog conversion (T-DAC) unit that includes a plurality of registers and a unary modulator (Umod) array. The T-DAC unit provides frequency selection ranges covering wide operational bands based on the digital pattern data and the clock signal.

Abstract: An RF signal source receives wideband digital signals representing the instantaneous amplitude of the desired RF, and ?? converts to ternary ?? signals. The ternary ?? signals are delayed in a transversal filter and the delayed signals are converted to currents for application to a traveling-wave summer for producing the desired RF. The traveling-wave summer may be a transmission line. The currents may be weighted with a filter response in order to limit the bandwidth of the RF signals. The RF may be coupled out through an antialiasing filter. The digital clocks may be delayed to correspond with the delays of the combiner, to impart directionality to the summed signals.

Abstract: A ?) analog-to-digital converter (ADC) includes an ADC converter element which receives resonated signals for generating output digital signals, and also a DAC for generating a reconstituted analog signal therefrom. A summer sums the reconstituted and input analog signals with filtered signals to generate resonated signals for the ADC element. A resonator includes a filter receiving the resonated signals, for producing the filtered signals for application to the summer. The summing circuit, the ADC element, and the digital-to-analog converter are in a first feedback loop, and the summer and the filter are in a second loop. The only coupling between the loops is the summing circuit. The delays of the loops become isolated from each other, and the overall performance of the sigma-delta ADC is dependent only on the longer of the two individual delays, rather than on the sum of the delays. This provides wider bandwidth A-D conversion (150).

Abstract: A sigma-delta analog-to-digital converter (10) provides high loop gain for suppression of noise components by use of a regenerative feedback loop or resonator (50), which produces a comb resonance response 212), embedded in the main degenerative feedback loop (48). The main loop includes an ADC (32) which samples at a clock frequency, which in turn defines a Nyquist frequency. The main loop also includes a DAC (38) which has a transfer function (42), which is equalized by a filter (44). The resonator (50) includes a low-pass filter (52) which matches the equalized main loop transfer function, a DC block (56), and a null filter (54) which nulls the resonator gain at the comb peak which lies above the Nyquist frequency. The open-loop transfer function of the regenerative loop (50) is set to unity gain and 0.degree..+-.N 360.degree. phase at the frequency of the analog input signal. A multipole embodiment (510) has multiple regenerative loops (55o) which produce multipole noise rejection (642).

Abstract: A sigma-delta (.SIGMA..DELTA.) analog-to-digital converter (ADC) accepts band-limited analog signals, and subtracts an analog replica of an output pulse- or amplitude-density modulated (ADM) signal therefrom to produce an error signal. The error signal is processed by an analog filter or resonator with a nondelayed forward path and a tapped nonaccumulating delay line, and summed feedback and feedforward weights coupled to the taps, to thereby produce a resonated signal. An ADC processes the resonated signal, and produces the ADM signal. The ADC undesirably produces quantization noise. A digital-to-analog converter (DAC) noiselessly converts the PDM signal into the analog replica, to aid in forming the error signal. In a particular embodiment of the invention, the resonator includes a recursive analog transversal filter with delays and linear weighting elements for linearity and high operating speed. The ADC may be in a high-speed system such as a radar.

Abstract: A beamformer for a main antenna and a plurality of auxiliary antennas converts the main and each of the auxiliary signals to digital form. Each of the real and auxiliary digital signals is applied to a pair of real multipliers, in which multiplication by beamforming weights is performed, to produce one weighted real main signal, one weighted imaginary main signal, and a plurality of weighted real and weighted imaginary auxiliary signals. The weighted real main and auxiliary signals are summed together by a cascade of summers, and the weighted imaginary main and auxiliary signals are likewise summed together by another summed cascade. A digital product detector is connected to the output of each summer cascade. The first digital product detector produces in-phase and quadrature components of real detected signals, and the second digital product detector produces in-phase and quadrature components of imaginary detected signals.