Patents by Inventor Leopoldo D. Yau
Leopoldo D. Yau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6326664Abstract: A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip comprising an ultra shallow region which extends beneath the gate electrode and a raised region.Type: GrantFiled: November 17, 1997Date of Patent: December 4, 2001Assignee: Intel CorporationInventors: Robert S. Chau, Chan-Hong Chern, Chia-Hong Jan, Kevin R. Weldon, Paul A. Packan, Leopoldo D. Yau
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Patent number: 6165826Abstract: A novel transistor with a low resistance ultra shallow tip region and its method of fabrication in a complementary metal oxide semiconductor (CMOS) process. According to the preferred method of the present invention, a first gate dielectric and a first gate electrode are formed on a first portion of a semiconductor substrate having a first conductivity type, and a second gate dielectric and a said gate electrode are formed on a second portion of semiconductor substrate having a second conductivity type. A silicon nitride layer is formed over the first portion of the semiconductor substrate including the first gate electrode and over the second portion of the semiconductor substrate including the second gate electrode. The silicon nitride layer is removed from the second portion of the silicon substrate and from the top of the second gate electrode to thereby form a first pair of silicon nitride spacers adjacent to opposite sides of the second gate electrode.Type: GrantFiled: December 29, 1995Date of Patent: December 26, 2000Assignee: Intel CorporationInventors: Robert S. Chau, Chia-Hong Jan, Chan-Hong Chern, Leopoldo D. Yau
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Patent number: 6139404Abstract: A semiconductor wafer polishing pad conditioner which includes a support structure and a roller which is rotatably mounted to the support structure. The roller has a working surface which is formed with a plurality of blades.Type: GrantFiled: January 20, 1998Date of Patent: October 31, 2000Assignee: Intel CorporationInventor: Leopoldo D. Yau
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Patent number: 6095904Abstract: A method and apparatus for polishing a thin film formed on a semiconductor substrate. A table covered with a polishing pad is orbited about an axis. Slurry is fed through a plurality of spaced-apart holes formed through the polishing pad to uniformly distribute slurry across the pad surface during polishing. A substrate is pressed face down against the orbiting pad's surface and rotated to facilitate, along with the slurry, the polishing of the thin film formed on the substrate.Type: GrantFiled: February 1, 1996Date of Patent: August 1, 2000Assignee: Intel CorporationInventors: Joseph R. Breivogel, Samuel F. Louke, Michael R. Oliver, Leopoldo D. Yau, Christopher E. Barns
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Patent number: 5863832Abstract: The present invention provides an interconnect system. The interconnect system includes a substrate, a first dielectric layer deposited upon the substrate. The interconnect system further includes at least two electrically conductive interconnect lines formed upon the first dielectric layer. Each of the at least two interconnect lines have a top surface and side surfaces. Adjacent side surfaces of two adjacent interconnect lines define therebetween a space that has a dielectric constant substantially equal to 1. A dielectric film is bonded upon the top surface of the at least two interconnect lines. The dielectric film substantially prevents obstruction of the space by further process.Type: GrantFiled: June 28, 1996Date of Patent: January 26, 1999Assignee: Intel CorporationInventors: Brian Doyle, Quat T. Yu, Leopoldo D. Yau
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Patent number: 5856697Abstract: A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in emitter mask thicknesses is disclosed. The polysilicon emitter isolation provides for better electrical breakdown characteristics between the emitter and the base by protecting the dielectric layer between the polysilicon emitter and base regions from defects and contamination associated with the BiCMOS manufacturing environment. The polysilicon emitter is trenched into the semiconductor substrate in order to reduce transistor operation problems associated with hot electron injection. Consistent base widths improve transistor performance uniformity thereby improving manufacturability and reliability.Type: GrantFiled: July 14, 1997Date of Patent: January 5, 1999Assignee: Intel CorporationInventors: Stephen Chambers, Brian J. Brown, Chan-Hong Chern, Robert Chau, Leopoldo D. Yau
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Patent number: 5783478Abstract: A novel, reliable, high performance MOS transistor with a composite gate electrode which is compatible with standard CMOS fabrication processes. The composite gate electrode comprises a polysilicon layer formed on a highly conductive layer. The composite gate electrode is formed on a gate insulating layer which is formed on a silicon substrate. A pair of source/drain regions are formed in the substrate and are self-aligned to the outside edges of the composite gate electrode.Type: GrantFiled: April 29, 1996Date of Patent: July 21, 1998Assignee: Intel CorporationInventors: Robert S. Chau, David B. Fraser, Kenneth C. Cadien, Gopal Raghavan, Leopoldo D. Yau
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Patent number: 5710450Abstract: A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip region comprising an ultra shallow region which extends beneath the gate electrode and a raised region.Type: GrantFiled: December 23, 1994Date of Patent: January 20, 1998Assignee: Intel CorporationInventors: Robert S. Chau, Chan-Hong Chern, Chia-Hong Jan, Kevin R. Weldon, Paul A. Packan, Leopoldo D. Yau
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Patent number: 5625217Abstract: A novel, reliable, high performance MOS transistor with a composite gate electrode which is compatible with standard CMOS fabrication processes. The composite gate electrode comprises a polysilicon layer formed on a highly conductive layer. The composite gate electrode is formed on a gate insulating layer which is formed on a silicon substrate. A pair of source/drain regions are formed in the substrate and are self-aligned to the outside edges of the composite gate electrode.Type: GrantFiled: February 2, 1995Date of Patent: April 29, 1997Assignee: Intel CorporationInventors: Robert S. Chau, David B. Fraser, Kenneth C. Cadien, Gopal Raghavan, Leopoldo D. Yau
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Patent number: 5611943Abstract: A method and apparatus for conditioning and/or rinsing a pad in a chemical-mechanical polisher. A scoring apparatus is rotated about its center directly over the polishing pad of the chemical-mechanical polisher. The scoring apparatus scores the pad surface while rotating above the pad. Consequently the pad is conditioned in a uniform and concentric fashion.Type: GrantFiled: September 29, 1995Date of Patent: March 18, 1997Assignee: Intel CorporationInventors: Kenneth C. Cadien, Leopoldo D. Yau
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Patent number: 5595526Abstract: A method for polishing the surface of a substrate that overcomes the problems inherent in the prior art. During the polishing of a substrate, a quantity is calculated which is approximately proportional to a share of the total energy the polisher is consuming. Once this calculated quantity reaches a predetermined amount, it is detected.Type: GrantFiled: November 30, 1994Date of Patent: January 21, 1997Assignee: Intel CorporationInventors: Leopoldo D. Yau, Paul B. Fischer
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Patent number: 5554064Abstract: A method and apparatus for polishing a thin film formed on a semiconductor substrate. A table covered with a polishing pad is orbited about an axis. Slurry is fed through a plurality of spaced-apart holes formed through the polishing pad to uniformly distribute slurry across the pad surface during polishing. A substrate is pressed face down against the orbiting pad's surface and rotated to facilitate, along with the slurry, the polishing of the thin film formed on the substrate.Type: GrantFiled: August 6, 1993Date of Patent: September 10, 1996Assignee: Intel CorporationInventors: Joseph R. Breivogel, Samuel F. Louke, Michael R. Oliver, Leopoldo D. Yau, Christopher E. Barns
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Patent number: 5488003Abstract: A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in emitter mask thicknesses is disclosed. The polysilicon emitter isolation provides for better electrical breakdown characteristics between the emitter and the base by protecting the dielectric layer between the polysilicon emitter and base regions from defects and contamination associated with the BiCMOS manufacturing environment. The polysilicon emitter is trenched into the semiconductor substrate in order to reduce transistor operation problems associated with hot electron injection. Consistent base widths improve transistor performance uniformity thereby improving manufacturability and reliability.Type: GrantFiled: March 31, 1993Date of Patent: January 30, 1996Assignee: Intel CorporationInventors: Stephen Chambers, Brian J. Brown, Chan-Hong Chern, Robert Chau, Leopoldo D. Yau
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Patent number: 5434093Abstract: A method for forming narrow length transistors by forming a trench in a first layer over a semiconductor substrate. Spacers are then formed within the trench and a gate dielectric is formed between the spacers at the bottom of the trench on the semiconductor substrate. The trench is then filled with a gate electrode material which is chemically-mechanically polished back to isolate the gate electrode material within the trench, and the first layer is removed leaving the gate dielectric, gate electrode and spacers behind.Type: GrantFiled: August 10, 1994Date of Patent: July 18, 1995Assignee: Intel CorporationInventors: Robert S. Chau, Chan-Hong Chern, Shahriar S. Ahmed, Robert F. Hainsey, Robert J. Stoner, Todd E. Wilke, Leopoldo D. Yau
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Patent number: 5244843Abstract: A novel process for forming a robust, sub-100 .ANG. oxide is disclosed. Native oxide growth is tightly controlled by flowing pure nitrogen during wafer push and nitrogen with a small amount of oxygen during temperature ramp and stabilization. First, a dry oxidation is performed in oxygen and 13% trichloroethane. Next, a wet oxidation in pyrogenic steam is performed to produce a total oxide thickness of approximately 80 .ANG.. The oxide layer formed is ideally suited for use as a high integrity gate oxide below 100 .ANG.. The invention is particularly useful in devices with advanced, recessed field isolation where sharp silicon edges are difficult to oxidize. For an oxide layer of more than 100 .ANG., a composite oxide stack is used which comprises 40-90 .ANG. of pad oxide formed using the above novel process, and 60-200 .ANG. of deposited oxide.Type: GrantFiled: December 17, 1991Date of Patent: September 14, 1993Assignee: Intel CorporationInventors: Robert S. K. Chau, William L. Hargrove, Leopoldo D. Yau
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Patent number: 5104819Abstract: A method and a device formed by the method of forming a composite dielectric structure between the floating polysilicon electrode and the control electrode of an EPROM-type device is disclosed. The dielectic is characterized by a thin (0-80 angstroms) thermally-grown or CVD bottom oxide layer covered by a relatively thin (<200 angstroms) silicon nitride layer. The top layer comprises a CVD oxide deposited in a thickness up to 150 angstroms. The capacitively measured effective thickness of the complete structure is about 200 .ANG. or less. The top layer CVD oxide has a thickness greater than the bottom oxide layer and greater than or equal to that of the silicon nitride layer and may also extend beyond the EPROM cell to form at least a part of the peripheral transistor dielectric.Type: GrantFiled: August 7, 1989Date of Patent: April 14, 1992Assignee: Intel CorporationInventors: Philip E. Freiberger, Leopoldo D. Yau, Cheng-Sheng Pan, George E. Sery
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Patent number: 4917044Abstract: An electrical contact apparatus for use in a plama or glow discharge chamber, particularly a chamber for depositing silicon oxynitride. A feedthrough member provides an electrical path between the interior and exterior of the chamber. An electrical contact member having an outwardly domed surface engages the feedthrough member. A non-conductive collar is disposed about the domed surface for limiting the flow of gas around the domed surface.Type: GrantFiled: June 2, 1989Date of Patent: April 17, 1990Assignee: Intel CorporationInventors: Leopoldo D. Yau, Galen H. Kawamoto
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Patent number: 4837185Abstract: A method of depositing a thin film of silicon oxynitride (Si.sub.x O.sub.y N.sub.z) onto a semiconductor substrate utilizing dual frequency plasma enhanced chemical vapor deposition (PECVD). Plasma formation is achieved by striking gases in a reaction chamber with a high voltage, low frequency radio wave, and then triggering and applying with the leading or trailing edge of the striking pulse, a second high frequency, low power radio wave. The plasma transfers energy into reactant gases forming a thin film of silicon oxynitride (Si.sub.x O.sub.y N.sub.z) onto a semiconductor substrate. The high frequency pulses provides more efficient gas ionization and less pattern, and back oxide sensitivity to film deposition rate.Type: GrantFiled: October 26, 1988Date of Patent: June 6, 1989Assignee: Intel CorporationInventors: Leopoldo D. Yau, Galen H. Kawamoto
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Patent number: 4786612Abstract: An improved resistor for use in MOS integrated circuits. An opening is formed in an insulative layer which separates two conductive regions. A plasma enhanced chemical vapor deposition of passivation material such as silicon-rich silicon nitride is deposited in the window, contacting both conductive regions and providing resistance in a vertical direction between these regions.Type: GrantFiled: December 29, 1987Date of Patent: November 22, 1988Assignee: Intel CorporationInventors: Leopoldo D. Yau, Shih-Ou Chen, Yih S. Lin
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Patent number: RE38674Abstract: A novel process for forming a robust, sub-100 Å oxide is disclosed. Native oxide growth is tightly controlled by flowing pure nitrogen during wafer push and nitrogen with a small amount of oxygen during temperature ramp and stabilization. First, a dry oxidation is performed in oxygen and 13% trichloroethane. Next, a wet oxidation in pyrogenic steam is performed to produce a total oxide thickness of approximately 80 Å. The oxide layer formed is ideally suited for use as a high integrity gate oxide below 100 Å. The invention is particularly useful in devices with advanced, recessed field isolation where sharp silicon edges are difficult to oxidize. For an oxide layer of more than 100 Å, a composite oxide stack is used which comprises 40-90 Å of pad oxide formed using the above novel process, and 60-200 Å of deposited oxide.Type: GrantFiled: September 14, 1995Date of Patent: December 21, 2004Assignee: Intel CorporationInventors: Robert S. K. Chau, William L. Hargrove, Leopoldo D. Yau