Abstract: A low power management system including both hardware and software is provided for a battery powered portable computer. The low power management system powers down various sections of the computer when they are not used. The low power management system is controlled by a control program in the microprocessor of the computer. The low power management system includes the capability to turn off clock signals to various sections of the computer based upon demand. Also included is the capability to turn on clock signals based upon demand. The low power management system also includes the capability to turn on the computer upon a press of a key on the computer keyboard. The low power management system monitors software application programs for keyboard activity so as to turn off the microprocessor in the computer in response to a loop looking for a keypress and certain other loops which can be monitored without use of the microprocessor.

Abstract: A low power management system including both hardware and software for a battery powered portable computer. The low power management system powers down various sections of the computer when they are not used. The low power management system is controlled by a control program in the microprocessor of the computer. The low power management system includes the capability to turn off clock signals to various sections of the computer based upon demand. Also included is the capability to turn on clock signals based upon demand. The low power management system also includes the capability to turn on the computer upon a press of a key on the computer keyboard. The low power management system monitors software application programs for keyboard activity so as to turn off the microprocessor in the computer in response to a loop looking for a keypress and certain other loops which can be monitored without use of the microprocessor.

Abstract: A calculator having constant memory utilizing a classical CMOS metal gate process, a low power microcomputer with on-chip and external constant memory capability. Incorporation of a switched negative voltage and a non-switched negative voltage to the appropriate P (-) wells enables the power hungry clocked logic to be turned off while power is maintained on the internal static RAM, on the digit latches, and on the R-lines which connect to both the internal and external RAM. Thus, semi-non-volatile memory (constant memory) capability may be achieved with a low standby current.