Patents by Inventor Lesley A. Polka Wood

Lesley A. Polka Wood has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SELECTIVE PROTECTION OF INTEGRATED CIRCUIT CHIP SURFACE REGIONS FROM UNDERFILL CONTACT
    Publication number: 20230084375
    Abstract: An apparatus comprising an integrated circuit chip comprising a first surface region and a second surface region adjacent to the first surface region; a substrate coupled to the integrated circuit chip through a plurality of connections comprising solder; and underfill between the substrate and the integrated circuit chip, wherein the underfill contacts the second surface region, but does not contact the first surface region.
    Type: Application
    Filed: September 14, 2021
    Publication date: March 16, 2023
    Applicant: Intel Corporation
    Inventors: Priyanka Dobriyal, Ankur Agrawal, Anna M. Prakash, Ann J. Xu, Jimin Yao, Raiyomand F. Aspandiar, Lesley A. Polka Wood, Abigail G. Agwai, Kayleen L. E. Helms
  • MICROELECTRONIC PACKAGE WITH REDUCED THROUGH-SUBSTRATE ROUTING
    Publication number: 20210296241
    Abstract: Embodiments may relate to a microelectronic package that includes an active die at a first side of the substrate and an interconnect at a second side of the substrate. A high-speed input/output (HSIO) die may also be coupled with the first side of substrate. The HSIO die may be coupled with the active die by a bridge. Other embodiments may be described or claimed.
    Type: Application
    Filed: March 20, 2020
    Publication date: September 23, 2021
    Applicant: Intel Corporation
    Inventors: Arghya Sain, Lesley A. Polka Wood, Russell K. Mortensen
  • In-package microelectronic apparatus, and methods of using same
    Patent number: 8354748
    Abstract: A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: January 15, 2013
    Assignee: Intel Corporation
    Inventors: Sriram Dattaguru, Lesley A. Polka Wood, Yoshihiro Tomita, Kiniya Ichikawa, Robert L. Sankman
  • IN-PACKAGE MICROELECTRONIC APPARATUS, AND METHODS OF USING SAME
    Publication number: 20120113704
    Abstract: A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s.
    Type: Application
    Filed: January 20, 2012
    Publication date: May 10, 2012
    Inventors: Sriram Dattaguru, Lesley A. Polka Wood, Yoshihiro Tomita, Kiniya Ichikawa, Robert L. Sankman
  • In-package microelectronic apparatus, and methods of using same
    Patent number: 8110920
    Abstract: A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: February 7, 2012
    Assignee: Intel Corporation
    Inventors: Sriram Dattaguru, Lesley A. Polka Wood, Yoshihiro Tomita, Kinya Ichikawa, Robert L. Sankman
  • In-pakage microelectronic apparatus, and methods of using same
    Publication number: 20100309704
    Abstract: A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s.
    Type: Application
    Filed: June 5, 2009
    Publication date: December 9, 2010
    Inventors: Sriram Dattaguru, Lesley A. Polka Wood, Yoshihiro Tomita, Kinya Ichikawa, Robert L. Sankman