Abstract: A floating point arithmetic unit that executes a single compound instruction that produces the result A+B.times.C with A, B and C being floating point numbers. Arithmetic on the exponents of A, B and C provide a normalized result of the multiplication before the addition takes place producing a normalized result of the compound instruction. The final normalized result is identical to a result that would be obtained by executing a separate instruction for the multiply, with normalized result, followed by an add instruction with a normalized result.

Abstract: A tree sorter having hardware logic node registers and output selectors plus comparators enables a vector processor to perform sort and merge operations. A system and method of providing one output record each cycle provides performance enhancement over similar scalar operation. Storage to storage traffic is drastically reduced because the hardware tree and update logic is implemented in the Vector Processor. Vector registers provide input data to the hardware tree structure. Output records sorted by key together with address ID are placed in storage. Multiple Vector count and multiple Vector Interruption Index (VIX) operation, string length and merge masks are used in conjunction with a vector merge instruction. The data input record key field has both long and short formats. Actual key data or codewords may be used. The vector merge forms a new codeword when compare equal codewords are encountered.

Abstract: A functional unit designed with arithmetic pipelining for vector processing is attached to a base data processor from which it receives vector instructions and operands for processing. Stepping of operands and exception indicators through the vector processing unit is controlled by the base processor. Exception information transferred to the base processor is controlled to provide precise indicators of error conditions for recovery and restart of vector processing. Masking logic provides for expansion/contraction of operands in the vector processing unit as compared with sequential main memory addresses.