Abstract: Method and apparatus are disclosed providing selective amplification of signals whereby signals exceeding a threshold voltage are amplified while signals below the threshold voltage are attenuated. The invention is preferably employed in a receiver of signals on an ISDN and reduces errors in the first data bit following framing bits. Furthermore, noise components in the received signals are attenuated. An operational amplifier (28) has an amplification determined by the ratio of a feedback resistance (30) to an input resistance. The input resistance consists of a first resistor (26), and a second resistor (24), which can be selectively placed in series with the first resistor. A pair of series-connected diode pairs (16, 18, 20, 22) are connected in parallel with the second resistor. One pair of series-connected diodes oriented oppositely to the other pair. The forward-biased saturation voltage of the series-connected pairs of diodes determine the threshold voltage of the non-linear amplifier.

Abstract: A preamble search and synchronizer circuit for detecting a preamble pattern within data input signals and synchronizing it with a clock signal associated with a StarLAN coded data transceiver includes a synchronizer start circuit, a counter circuit, and a pattern detector circuit. The synchronizer start circuit is responsive to the complement of the data input signals and the clock signal for generating a start signal which is synchronized with the clock signal. The counter circuit is responsive to the start signal and the complement of the clock signal for generating a gated clock signal. The pattern detector circuit is responsive to the start signal, the data input signals and the gated clock signal for sampling of the data input signals and for generating a synchronized output signal upon detection of a predetermined data sequence indicative of the preamble pattern.

Abstract: A digital filter receive circuit for use with a StarLAN coded data transceiver includes three D-type flip-flops and four NAND logic gates. The digital receive line filter circuit is capable of being implemented as part of a single monolithic integrated circuit containing the transceiver, thereby producing a miniaturized and compact structure.

Abstract: A daisy chain collision detection circuit for use with a StarLAN coded data transceiver includes a voltage comparator having an inverting input, a non-inverting input and an output. The inverting input of the voltage comparator is responsive to differential output voltages from a differential line drive and transient spike voltages from the primary of an isolation transformer. A charging capacitor is connected to the non-inverting input of the voltage comparator. The capacitor is charged to a reference voltage which is directly proportional to the peak voltage of the differential output voltages. The output of the voltage comparator provides an internal collision detection signal which is switched from a high logic level to a low logic level upon the occurrence of a daisy chain collision.