Abstract: A silicon controlled rectifier electrostatic discharge protection circuit with external on-chip triggering and compact internal dimensions for fast triggering. The ESD protection circuit includes a silicon controlled rectifier (SCR) having an anode coupled to the protected circuitry and a cathode coupled to ground, where the cathode has at least one high-doped region. At least one trigger-tap is disposed proximate to the at least one high-doped region and an external on-chip triggering device is coupled to the trigger-tap and the protected circuitry.

Abstract: A silicon controlled rectifier electrostatic discharge protection circuit with external on-chip triggering and compact internal dimensions for fast triggering. The ESD protection circuit includes a silicon controlled rectifier (SCR) having an anode coupled to the protected circuitry and a cathode coupled to ground, where the cathode has at least one high-doped region. At least one trigger-tap is disposed proximate to the at least one high-doped region and an external on-chip triggering device is coupled to the trigger-tap and the protected circuitry.

Abstract: An ESD protection circuit includes a portion for protecting a pair of power lines and a portion for protecting an input/output pin. The power line protection portion includes at least three SCRs electrically connected in series between the power lines. A zener diode is electrically connected between a gate of the SCR at one end of the series and the negative power line, and a resistor is electrically connected between the gate of the one SCR and the positive power line. The gates of the other SCRs in the series are electrically connected to the negative power line or to their own cathode. The I/O pin protection portion includes a plurality of SCRs connected in series between the power lines with the I/O pin being connected between the SCR at one end of the series and the next adjacent SCR in the series. A separate zener diode is electrically connected between the gate of the SCR at the one end of the series and the gate of the next adjacent SCR and the negative power line.

Abstract: An ESD protection circuit includes a portion for protecting a pair of power lines and a portion for protecting an I/O pin. The power line protection portion includes at least three SCRs electrically connected in series between the power lines. A zener diode is electrically connected between a gate of the SCR at one end of the series and the negative power line, and a resistor is electrically connected between the gate of the one SCR and the positive power line. The gates of the other SCRs in the series are electrically connected to the negative power line or to their own cathode. The I/O pin protection portion includes a plurality of SCRs connected in series between the power lines with the I/O pin being connected between the SCR at one end of the series and the next adjacent SCR in the series. A separate zener diode is electrically connected between the gate of the SCR at the one end of the series and the gate of the next adjacent SCR and the negative power line.

Abstract: An electrostatic discharge (ESD) protection circuit for an integrated circuit formed of a plurality of individual circuit cells which are connected to form the desired circuit. A pair of buss lines, preferably in closely spaced relation, extend about the circuit formed by the circuit cells. A plurality of ESD protection circuits are electrically connected between the buss lines in a spaced apart relationship, preferably in a closed in a close relationship to the electrical connections of the circuit cells to be protected.

Abstract: An electrical circuit including an NMOS or lateral NPN bipolar transistor includes a zener diode connected thereto to provide ESD protection for the transistor. The NMOS transistor includes an N-type source, an N-type drain, a P-type channel region and a gate over and insulated from the channel region. The zener diode is electrically connected between the gate and the drain of the NMOS transistor with the anode of the zener diode being connected to the gate and the cathode of the zener diode being connected to the drain. For some purposes the anode of the zener diode is positioned close to the gate to provide the desired ESD protection. The lateral NPN bipolar transistor includes an N-type emitter and collector and a P-type base. The zener diode is connected between the collector and the base with the anode of the zener diode being connected to the base and the cathode of the zener diode being connected to the emitter.

Abstract: The invention is a protection circuit for an integrated circuit which includes an SCR switch, a zener diode in parallel with the SCR to trigger the SCR to its on-state, and a zener diode in series with the SCR controls the on-state or clamping voltage of the SCR. The protection circuit is formed in a semiconductor substrate of first conductivity type having a well region of second conductivity type, a first region of first conductivity type in the well and a second region of second conductivity type in the substrate spaced from the well region. The first region, well region, substrate and second region forming the SCR. A third region of second conductivity type is in the well region and contacts the first region to form a first zener diode. A fourth region of second conductivity type is in the substrate and electrically connected to the well region. A fifth region is in the substrate and contacts the fourth region to form a second zener diode.

Abstract: A low breakdown voltage device for protecting an integrated circuit from transient energy is disclosed. This device provides an SCR having a reduced "snap-back" trigger voltage compatible with submicron integrated circuit fabrication processes. A low breakdown voltage SCR protection circuit is also disclosed.

Abstract: A device for protecting an integrated circuit from transient energy is disclosed. This device provides an SCR having a reduced "snap-back" trigger voltage.

Abstract: A protection device for an integrated circuit includes short and longer channel length structures, each of which provides a parasitic bipolar transistor, connected between a terminal of the integrated circuit and a source of reference voltage. The short channel length structure has a breakdown voltage greater than the supply voltage for the integrated circuit, and less than the insulator damage threshold of the integrated circuit. The conduction through the short channel length structure after initiation of a transient phenomena causes the longer channel length structure to conduct before the transient exceeds the breakdown voltage of the integrated circuit and the short channel length structure. The longer channel length structure operatges in the "snap-back" conduction mode when the current density exceeds a critical value to conduct away the transient energy.

Abstract: A protection structure comprises a semiconductor substrate of a first conductivity type with a region of second conductivity type in the substrate at the surface thereof. A region of second conductivity type has disposed therein first and second regions of the second conductivity type, a third region of the first conductivity type adjacent the surface of the substrate, and a fourth region of the second conductivity type adjacent the substrate surface adjacent the third region. A shallow field region extends a distance into the region of second conductivity type between the first and second regions. A first electrical contact overlies the surface of the first region and a second electrical contact overlies the third and fourth regions.

Abstract: An integrated circuit includes a substrate of one conductivity type silicon and an epitaxial layer of the opposite conductivity type silicon on a surface of the substrate. An emitter region of the one conductivity type is in the epitaxial layer and a collector region of the one conductivity type is in the epitaxial layer and extends around but is spaced from the emitter region. A third region of the one conductivity type is in the epitaxial layer and extends partly around and is spaced from the collector region. A highly conductive connector region of the opposite conductivity type extends into the epitaxial layer to a buried region of the opposite conductivity type which is along the junction of the epixtaxial layer and the substrate. The connector region contacts the third region. A thin layer of silicon oxide extends over the epitaxial layer. Separate contacts extend through the epixtaxial layer to the emitter region, collector region and to adjacent portions of the third region and the collector region.

Abstract: A zener diode structure for integrated circuits is disclosed. The device includes a pair of opposing zener diodes separated by a parasitic resistance. The zener breakdown junctions of the two diodes are well below the surface of the device thereby reducing any adverse effect of stray surface charges and ultraviolet radiation. Further, the doping levels of the opposing diodes are selected to reduce drift in the breakdown voltage due to variations in operating temperature of the device.

Abstract: A protection circuit comprises first and second circuit to respectively protect an IC against negative and positive going transients in an input signal. If the input includes a repetitive signal greater than a threshold for firing the negative going protection circuit, substrate current injection and signal clamping will result. To prevent this, the first circuit includes an emitter-base shunt resistor and a Zener diode coupled to a pair of opposite conductivity type transistors to lower the threshold thereof. Each of the circuits comprises a pair of opposite conductivity type transistors formed in a single isolated region, which in turn is formed in an opposite conductivity type substrate.

Abstract: A zener diode structure for integrated circuits is disclosed. The device includes a pair of parallel zener diodes connected back to back with a third zener diode. The anode of one of the parallel diodes is connected to the anodes of the other two diodes through a parasitic resistance. The zener breakdown junctions of two of the diodes are well below the surface of the device thereby reducing any adverse affect of stray surface charges and ultraviolet radiation. Further, the doping levels of the opposing diodes are selected to reduce drift in the breakdown voltage due to variations in operating temperature of the device.

Abstract: The protection circuit is a four layer PNPN device which includes a PMOS IGFET. The device is designed to pass current to ground when large transients are imposed across its two external terminals, thereby protecting the integrated circuit.

Abstract: Disclosed is a protection circuit which may be used, for example, in a television receiver to protect circuitry inside an integrated circuit from damage due to high voltage transients. The protection circuit comprises a PNPN structure forming a silicon control rectifier (SCR) and a resistive element integral to the SCR structure. In one embodiment the resistive element is a linear resistor and in another embodiment is a non-linear resistor in the form of a diode connected transistor. The SCR and the resistive element are arranged to form a two terminal, high current protection circuit which is rendered conductive when the potential difference across the two terminals is greater than one forward biased PN junction voltage drop. One terminal of the protection circuit is connected to an input or output terminal of the protected circuit, and the other terminal is connected to the most positive power supply potential.

Abstract: A pair of protection circuits, each forming a silicon controlled rectifier (SCR) for protecting a circuit against either negative or positive voltage transients, are formed in a single isolated region together with a bond pad. A second embodiment also includes a sense resistor in the isolated region.

Abstract: A semiconductor device utilized in a monolithic integrated circuit for protection against large voltage transients comprises back-to-back zener diodes formed by two separate regions of one type conductivity extending through an epitaxial layer of the opposite type conductivity and contacting a buried pocket of the opposite type conductivity to form PN junctions therewith. In the preferred embodiment, one of the one-type-conductivity regions completely surrounds the other region of one type conductivity.

Abstract: Disclosed is a protection circuit which may be used, for example, in a television receiver to protect circuitry formed within an integrated circuit from damage due to excessively high voltage transients. The protection circuit comprises a PNPN structure forming a silicon controlled rectifier (SCR) and metal-oxide-semiconductor (MOS) transistor integral to the SCR structure. The SCR and the MOS transistors are arranged to form a two terminal protection circuit which is rendered conductive when the potential difference across the two terminals is greater than a predetermined threshold. One terminal of the protection circuit is connected to an input or output signal terminal of the protected circuit, and the other terminal is connected to a reference terminal to which a reference potential such as ground potential is applied.