Abstract: An ESD protection circuit includes a SCR and a switching means, such as a MOS transistor connected to the SCR so that the SCR is turned on by the switching means to allow an ESD pulse to pass from a Pad line to a grounded VSS line and thereby dissipate the ESD pulse. The SCR is connected between the Pad line and the VSS line. One MOS switching means is connected between the Pad line and the SCR and has a gate which is connected to a VDD line which maintains the switch in open condition during normal VDD bias conditions. An ESD pulse applied to the Pad line, the switch is preconditioned in ON mode allowing the SCR to be predisposed to conduction to allow the ESD pulse to flow to the VSS line.

Abstract: An exemplary embodiment of the invention eliminates the common P-Well in a stacked SCR structure by providing isolated P-Wells. This embodiment is particularly advantageous in electrostatic protection devices (ESD) formed from a plurality of silicon controlled rectifiers connected in series. The isolated P-Wells are formed, in part, by a high voltage CMOS process incorporating a relatively heavily doped retrograde buried N layer that enables the formation of junction isolated P-Wells surrounded by an N-Well. The complete isolation of the P-Well prevents the normal P-Well to P substrate short, enabling more effective triggering of stacked SCRs. Advantages of implementing isolated P-Wells over a common P-Well in a stacked SCR electrostatic protection device, include faster triggering, lower current triggering, and a reduction in the number of triggering structures required. These advantages are desirable for deep sub-micron ESD protection structures.

Abstract: An electrostatic protection (ESD) circuit for an integrated circuit (IC) includes a string of a plurality of diodes connected between a Vss line and a Vdd line. A first PMOS transistor and a first NMOS transistor are connected in series between the Vdd line and the string of diodes. The first PMOS transistor has a gate connected between two of the diodes of the string, and the NMOS transistor has a gate connected to the Vdd line. A second PMOS transistor and a second NMOS transistor are connected in series between the Vss line and the Vdd line with the PMOS transistor having a gate connected to the junction between the first PMOS transistor and the first NMOS transistor and the second NMOS transistor having a gate connected to the Vdd line. A clamp NMOS transistor is connected between the Vss line and the Vdd line and has a gate connected to the junction between the second PMOS transistor and the second NMOS transistor. A diode may be connected between the Vdd line and the second PMOS transistor.

Abstract: A circuit for the protection of an output driver NMOS transistor during EOS/ESD stress includes an output driver NMOS transistor and an output driver PMOS transistor connected in series between a Vss line and a Vdd line with the gates of the output driver transistors being connected together. An I/O pad is connected to the junction of the output driver transistors. A pre-driver NMOS transistor and a pre-driver PMOS transistor are connected in series between the Vss line and the Vdd line with the gates of the out-put driver transistors being connected together with the output of the pre-driver transistors being connected to the gates of the output driver transistors. A gate clamp is connected between the Vss line, the I/O pad the junction between the pre-driver transistors and the gate of the output driver NMOS transistor. An ESD clamp is connected between the I/O pad, the Vss line and the gate clamp.

Abstract: Apparatus for providing electrostatic discharge protection having an nMOS transistor with bias simultaneously applied to the gate and the p-well of the nMOS transistor. A bias circuit is fabricated using a plurality of the Zener diodes. The double bias allows for a relatively high gate voltage to be applied to the nMOS transistor enabling the nMOS transistor to be biased to optimum conditions for bipolar snapback.

Abstract: An integrated circuit system includes a substrate of an electrical insulating material having a surface. Mounted on the surface of the substrate is an IC, a semiconductor piece having therein a circuit, such as a microprocessor, having a plurality of functional blocks. Also mounted on the substrate are a plurality of power supply chips. Each of the power supply chips is connected through conductors and vias in the substrate to a separate functional block on the IC semiconductor piece. Each of the power supply chips forms part of a circuit, such as a DC-DC converter, which is capable of reducing a voltage supplied thereto to a lower voltage suitable for the particular functional block to which the particular power supply chip is connected. Thus, a single relatively large voltage fed to the power supply chips through conductors on the substrate is reduced by each power supply chip to a lower voltage suitable for the particular functional block of the IC semiconductor piece.

Abstract: An integrated circuit system includes a substrate of an electrical insulating material having a surface. Mounted on the surface of the substrate is an IC, a semiconductor piece having therein a circuit, such as a microprocessor, having a plurality of functional blocks. Also mounted on the substrate are a plurality of power supply chips. Each of the power supply chips is connected through conductors and vias in the substrate to a separate functional block on the IC semiconductor piece. Each of the power supply chips forms part of a circuit, such as a DC-DC converter, which is capable of reducing a voltage supplied thereto to a lower voltage suitable for the particular functional block to which the particular power supply chip is connected. Thus, a single relatively large voltage fed to the power supply chips through conductors on the substrate is reduced by each power supply chip to a lower voltage suitable for the particular functional block of the IC semiconductor piece.

Abstract: A crisscross level shifter comprising a pull-down circuit configured as a pair of cascode amplifiers and a crisscross pull-up circuit. The cascode amplifiers are enhanced by a feedforward circuit coupling, for both amplifiers, the input of one cascode amplifier to the output of the other cascode amplifier.

Abstract: An ESD protection circuit includes a pair of NPN lateral transistors electrically connected in series with the emitter of one of the transistors electrically connected to the collector of the other transistor. The bases of the two transistors are electrically connected together and are floating. The two transistors may be provided by two MOS transistors having N-type source and drains and P-type channel regions. The channels regions are connected together and are floating.

Abstract: An electrostatic discharge (ESD) protection circuit includes an input terminal, a power supply line and a source of reference potential. The circuit also includes a dummy supply line. A Schottky barrier diode is connected between the input terminal and the power supply line for blocking voltages from the input terminal which are greater than the power supply voltage. A first clamping structure is connected between the dummy supply line and the source of reference potential, and a second clamping structure is connected between the power supply line and the source of reference potential. A first clamping diode is connected between the input terminal and the dummy supply line and a second clamping diode is connected between the input terminal and the source of reference potential.

Abstract: A constant current source supplies a bias current through a diode chain, establishing a first voltage at a terminal coupled to the string. A DC restorer circuit, responsive to a source of composite video signals, couples an additional current through the diode chain during the sync interval. This additional current establishes a second voltage level at the terminal. The second voltage is compared with a reference voltage for producing output signals synchronized with the sync pulses.

Abstract: A synchronizing signal amplifier which has an input terminal coupled to a source of synchronizing signals and noise signals by means of a capacitor has its common terminal coupled to reference potential by means of a switching circuit having its input terminal coupled to the source of synchronizing signals and noise signals. When signals produced by the source of synchronizing signals and noise signals are less than a noise threshold level established by the switching means, the common terminal of the amplifier is coupled to reference potential by the switching means and the current through the capacitor is basically a function of the input impedance of the amplifier.

Abstract: A color kinescope matrix amplifier has a first input coupled through a capacitor to a source of color difference signals. Another input is coupled to a source of luminance signals. The matrix amplifier includes a cascode output stage direct current coupled to a cathode of a kinescope. A portion of a direct voltage developed at the cascode output amplifier is coupled to one input of a comparator circuit. The other input of the comparator circuit is coupled to a temperature compensated direct voltage reference source. The comparator is rendered operative during horizontal retrace intervals to provide a current to either charge or discharge the input capacitor in accordance with the difference between the voltage at the output of the cascode output amplifier and the reference voltage to compensate for voltage variations at the output of the cascode amplifier due to power supply variations and the like.

Abstract: Constant width drive pulses developed by a pulse generator are shifted in phase relative to control signals locked to synchronizing signals to maintain a predetermined phase relationship between deflection signals produced by a deflection circuit and the control signals.