Abstract: A method and circuit for generating a commutate signal required to control the spindle motor. The spindle motor generates a BEMF signal which transitions periodically between states. This signal is used to generate a synchronizing pulse at the transitions of the BEMF signal. The synchronizing pulse resets a counter which incrementally counts a value at each clock pulse of the circuit. When a BEMF transition is received, a maximum count value for the BEMF period is determined and the counter is reset to zero. The maximum count value is then divided in half, preferably by a right shifting binary representation of the maximum count value by one bit, thereby dividing the value by one-half, and is input to a register. The value equal to one-half of the maximum count value is then outputted from the register at each subsequent clock pulse to a comparator. Also output is the current count generated by the counter. Thus when the curent counter value equals the value stored in the register, a pulse is generated.

Abstract: A test management system acquires, processes and displays test data. A control processor operating system operates independently of a disk file server operating system to control the operation. The test data is received from any analog signal lines which are sampled at predetermined rates and digitized or received as digital data. The digital data is collected and stored in a random access memory. A control processor analyzes the data and displays the analyzed data on a monitor. The digital data and analyzed data may be stored on disk. The digitized data may be sampled to determine if predetermined limits are exceeded and control signals may be sent back to the originating signal generator indicating corrective action.

Abstract: In a magnetic tape recording/playback system, there has here been provided a phase sensor circuit wherein a recorded square wave signal, when played back, produces a signal which includes a predominant first and third harmonic. A filtered sample of the relative amplitude of the resulting peaks is compared and a difference signal is indicative of a phase shift error. That signal may then be used to effect a control to correct the phase shift error.

Abstract: A Split Phase Bi-polar Date Receiver is contemplated which uses an Interval Detector to measure the time interval between excursions of the bi-polar signal away from zero. This time interval or bit period is compared to predetermined intervals associated with different types of received bits, i.e., data, synch, etc. A Synchronizing Pulse Counter is provided to enable the receiver only if a specific number of synch pulses have been received indicating that a valid message is following. The enabling signal conditions a Data Clocking Path and allows the data bits to be accepted by, stored-in, and read-out of the Receiver Data Register. If the incoming data bits are of the proper duration, the Time Interval Detector produces an output data pulse which together with the enabling signal from the Synchronization Counter allows the data bits to be entered into the Register.