Patents by Inventor Lester L. Wilson

Lester L. Wilson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7898275
    Abstract: An apparatus for testing a semiconductor die and the method wherein there is provided a package having a cavity therein with a plurality of terminals in the package disposed at the periphery of the cavity. A semiconductor die to be tested and having a plurality of bond pads thereon is disposed in the cavity and an interconnecting layer having electrically conductive paths thereon is also disposed in the cavity, each of the paths having first and second spaced apart regions thereon, the first region of each path being aligned with and contacting a bond pad. An interconnection is provided between the second spaced apart region of each of the paths and one of the plurality of terminals. The second spaced apart region of each of the paths is preferably a bump aligned with and contacting one of the plurality of terminals. A compliant layer is preferably disposed over the interconnecting layer and provides a force causing engagement of at least the first spaced apart regions and the bond pads.
    Type: Grant
    Filed: October 1, 1998
    Date of Patent: March 1, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Richard W. Arnold, Weldon Beardain, Daniel W. Prevedel, Donald E. Riley, Lester L. Wilson
  • Patent number: 7122895
    Abstract: A method of forming a membrane for use in conjunction with a semiconductor carrier and the membrane which includes an electrically insulating substrate and an interconnect pattern formed on the substrate. A stud is coupled to the interconnect pattern over the substrate by forming a gold ball, preferably by gold ball bonding techniques, and coating a portion of the gold ball with a compliant material, preferably an epoxy resin. The coating is filled with a material having sufficient hardness to be capable of penetrating the oxide film on the contact pads of semiconductor devices. The flakes are preferably silver or silver-based.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: October 17, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Richard W. Arnold, Weldon Beardain, Lester L. Wilson, James A. Forster
  • Publication number: 20040152232
    Abstract: A method of forming a membrane for use in conjunction with a semiconductor carrier and the membrane which includes an electrically insulating substrate and an interconnect pattern formed on the substrate. A stud is coupled to the interconnect pattern over the substrate by forming a gold ball, preferably by gold ball bonding techniques, and coating a portion of the gold ball with a compliant material, preferably an epoxy resin. The coating is filled with a material having sufficient hardness to be capable of penetrating the oxide film on the contact pads of semiconductor devices. The flakes are preferably silver or silver-based.
    Type: Application
    Filed: May 1, 2001
    Publication date: August 5, 2004
    Inventors: Richard W. Arnold, Weldon Beardain, Lester L. Wilson, James A. Forster
  • Patent number: 6720574
    Abstract: An apparatus for testing a semiconductor die and the method wherein there is provided a package having a cavity therein with a plurality of terminals in the package disposed at the periphery of the cavity. A semiconductor die to be tested and having a plurality of bond pads thereon is disposed in the cavity and an interconnecting layer having electrically conductive paths thereon is also disposed in the cavity, each of the paths having first and second spaced apart regions thereon, the first region of each path being aligned with and contacting a bond pad. An interconnection is provided between the second spaced apart region of each of the paths and one of the plurality of terminals. The second spaced apart region of each of the paths is preferably a bump aligned with and contacting one of the plurality of terminals. A compliant layer is preferably disposed over the interconnecting layer and provides a force causing engagement of at least the first spaced apart regions and the bond pads.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: April 13, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Richard W. Arnold, Weldon Beardain, Daniel W. Prevedel, Donald E. Riley, Lester L. Wilson
  • Patent number: 6489673
    Abstract: A package for a semiconductor die having a header with a cavity. The cavity includes a floor, sidewalls and a plurality of vertically spaced apart rows along the cavity sidewalls, each row including a plurality of spaced apart bond fingers. An electrically insulating membrane, preferably silicon, is disposed over the floor of the cavity, the membrane including a plurality of bumps, a plurality of peripherally located membrane bond pads and an interconnect from each of the bumps to a membrane bond pad. Bond wires are connected between the membrane bond pads and the bond fingers on the plurality of rows. A semiconductor die is provided having a plurality of bond pads, each bond pad contacting one of the bumps on the membrane. The header includes a plurality of alternating layers of electrically conducting material and electrically insulating material, the bond fingers on the header each being coupled to one of the layers of electrically conducting material.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: December 3, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Richard W. Arnold, Lester L. Wilson, Mahmood A. Siddiqui, James A. Forster
  • Publication number: 20020084515
    Abstract: An apparatus for testing a semiconductor die and the method wherein there is provided a package having a cavity therein with a plurality of terminals in the package disposed at the periphery of the cavity. A semiconductor die to be tested and having a plurality of bond pads thereon is disposed in the cavity and an interconnecting layer having electrically conductive paths thereon is also disposed in the cavity, each of the paths having first and second spaced apart regions thereon, the first region of each path being aligned with and contacting a bond pad. An interconnection is provided between the second spaced apart region of each of the paths and one of the plurality of terminals. The second spaced apart region of each of the paths is preferably a bump aligned with and contacting one of the plurality of terminals. A compliant layer is preferably disposed over the interconnecting layer and provides a force causing engagement of at least the first spaced apart regions and the bond pads.
    Type: Application
    Filed: November 8, 2001
    Publication date: July 4, 2002
    Inventors: Richard W. Arnold, Weldon Beardain, Daniel W. Prevedel, Donald E. Riley, Lester L. Wilson
  • Patent number: 6376352
    Abstract: A method of forming a membrane for use in conjunction with a semiconductor carrier and the membrane which includes an electrically insulating substrate and an interconnect pattern formed on the substrate. A stud is coupled to the interconnect pattern over the substrate by forming a gold ball, preferably by gold ball bonding techniques, and coating a portion of the gold ball with a compliant material, preferably an epoxy resin. The coating is filled with a material having sufficient hardness to be capable of penetrating the oxide film on the contact pads of semiconductor devices. The flakes are preferably silver or silver-based.
    Type: Grant
    Filed: November 1, 1999
    Date of Patent: April 23, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Richard W. Arnold, Weldon Beardain, Lester L. Wilson, James A. Forster
  • Patent number: 6335226
    Abstract: A package for a semiconductor die having a header with a cavity. The cavity includes a floor, sidewalls and a plurality of vertically spaced apart rows along the cavity sidewalls, each row including a plurality of spaced apart bond fingers. An electrically insulating membrane, preferably silicon, is disposed over the floor of the cavity, the membrane including a plurality of bumps, a plurality of peripherally located membrane bond pads and an interconnect from each of the bumps to a membrane bond pad. Bond wires are connected between the membrane bond pads and the bond fingers on the plurality of rows. A semiconductor die is provided having a plurality of bond pads, each bond pad contacting one of the bumps on the membrane. The header includes a plurality of alternating layers of electrically conducting material and electrically insulating material, the bond fingers on the header each being coupled to one of the layers of electrically conducting material.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: January 1, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Richard W. Arnold, Lester L. Wilson, Mahmood A. Siddiqui, James A. Forster
  • Publication number: 20010030360
    Abstract: A package for a semiconductor die having a header with a cavity The cavity includes a floor, sidewalls and a plurality of vertically spaced apart rows along the cavity sidewalls, each row including a plurality of spaced apart bond fingers. An electrically insulating membrane, preferably silicon, is disposed over the floor of the cavity, the membrane including a plurality of bumps, a plurality of peripherally located membrane bond pads and an interconnect from each of the bumps to a membrane bond pad Bond wires are connected between the membrane bond pads and the bond fingers on the plurality of rows. A semiconductor die is provided having a plurality of bond pads, each bond pad contacting one of the bumps on the membrane. The header includes a plurality of alternating layers of electrically conducting material and electrically insulating material, the bond fingers on the header each being coupled to one of the layers of electrically conducting material.
    Type: Application
    Filed: June 15, 2001
    Publication date: October 18, 2001
    Inventors: Richard W. Arnold, Lester L. Wilson, Mahmood A. Siddiqui, James A. Forster
  • Patent number: 6209532
    Abstract: A method of transferring a semiconductor die from a wafer containing a plurality of semiconductor dice. There is provided a semiconductor wafer having a top side and an opposing bottom side and a plurality of dice formed therein, each die containing a portion of the top side and the opposing bottom side. The wafer is removably secured to a support and the wafer is operated upon to form individual dice on the support. The support is preferably a flexible film. A tool is disposed between the support and the bottom side of a the die by creating a vacuum between the tool and the bottom side to cause adherence of the die to the tool and the die is removed from the support with the tool and placed in a die carrier with the top side facing the carrier and the vacuum is then released. The film, when flexible, is stretched to separate the dice from each other and create streets between adjacent dice so that the tool can be disposed under the die from the street.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: April 3, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Richard W. Arnold, Lester L. Wilson