Abstract: A telephone test system (2) includes a controller (4), a programmable gate array (PGA) (24) and a digital signal processor (DSP) (26) connected by a common bus (20). The PGA (24) includes an output connected to an input of a digital-to-analog converter (DAC) (36) and input connected to an output of an analog-to-digital converter (ADC) (32). A driver circuit (46) is connected between the DAC (36) and a telephone circuit (60) and between the ADC (32) and the telephone circuit (60). Under the control of the DSP (26), the driver circuit (46) generates voltages to the telephone circuit (60) and samples the response of the telephone circuit (60) to such generated voltages. The driver circuit (46) includes control inputs for receiving from the PGA (24) an impedance adjust signal (D) and a resistance adjust signal (R). An output impedance (124) of the driver circuit (46) connected to the telephone circuit (60) is adjustable as a function of the impedance adjust signal (D) and/or the resistance adjust signal (R).

Abstract: A method using replication of distributed arithmetic logic circuits and recursive interpolation of reduced angular increments of sine and cosine sum constants in logic look-up tables, permits the computation of vector rotation and large FFTs in a unitary field programmable gate array chip without required off-chip memory for storing constants.

Abstract: A method using replication of distributed arithmetic logic circuits and recursive interpolation of reduced angular increments of sine and cosine sum constants in logic look-up tables, permits the computation of vector rotation and large FFTs in a unitary field programmable gate array chip without required off-chip memory for storing constants.

Abstract: A Lofargram Enhancement System having a processor having 1 to i rows and 1 to j columns of processing elements or data cells. Each data cell has a location corresponding to an index, a computational capability and a memory means for storing a a pixel intensity value. The memory cells of all processing elements are addressed concurrently. A FIFO receives and stores a scan line comprising a sequence of pixel intensity signal values. A program provides a means for calculating row and column total values for the total of the pixel intensity signal values stored in a predetrmined relationally related location for each respective processing element for each respective processing element in the systolic processor. An auxiliary processor reads the respective row total and column totals for each processing element in the jth column of the systolic processor and loads the corresponding first column processing element with a corrected pixel value.

Abstract: An analog-to-digital converter circuit receives an input signal of a first polarity and a reference voltage of a second polarity. The circuit has a first binary comparator with a resistor divider network connected between the input signal and the reference voltage. The first stage provides a most significant bit signal in response to the absolute value of the input signal exceeding one half the absolute value of the reference voltage. The circuit has at least a second binary bit stage. Each successive binary stage is responsive to the signal voltage and to the logic binary value of all higher order stages. The first and subsequent binary stage provides a binary coded signal with a value corresponding to the ratio of the value of input signal with respect to the value of the reference voltage. The first and second binary stages each have a binary comparator with a first polarity input connected to a reference potential.

Abstract: A frequency synthesizer for use by an operator or other means for continuously generating an output noise signal, the frequency synthesizer comprises a digital means for directly synthesizing random noise having controlled spectral amplitudes. The synthesized random noise is characterized by a series of digital composite frequency synthesizer output noise signal sample values. The digital means comprises a means for providing and for periodically changing a series of sets of shifted segment frequency values, each set of shifted segment frequency values having a controlled series of random frequency values. Each frequency value is a random digital number selected to be within a range corresponding to a segment frequency band and characterizes a shifted segment frequency value. A plurality of digital oscillators is included, each oscillator having a corresponding segment frequency band.