Patents by Inventor Lester Yeh

Lester Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Impedance adjustable circuit having on-chip adjustable termination resistor
    Patent number: 7345504
    Abstract: An adjustable termination resistor includes a reference resistor, a current mirror circuit, a calibration transistor-resistor array, a digital code generator, a comparator, a decision and latch circuit and a termination resistor. The mirror current generated from the current mirror circuit flows through the calibration transistor-resistor array to result in a comparing voltage across the calibration transistor-resistor array. The resistance of the calibration transistor-resistor array is determined according to a digital code generated from the digital code generator. The voltage level outputted from the comparator is changed from a first state to a second state when the digital code generator up counts to a target digital code such that the comparing voltage is just greater than the reference voltage. The decision and latch circuit records the target digital code into therein. The resistance of the termination resistor is adjustable according to the target digital code.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: March 18, 2008
    Assignee: Via Technologies, Inc.
    Inventors: Joanna Lin, Lester Yeh
  • IMPEDANCE ADJUSTABLE CIRCUIT HAVING ON-CHIP ADJUSTABLE TERMINATION RESISTOR
    Publication number: 20070040716
    Abstract: An adjustable termination resistor includes a reference resistor, a current mirror circuit, a calibration transistor-resistor array, a digital code generator, a comparator, a decision and latch circuit and a termination resistor. The mirror current generated from the current mirror circuit flows through the calibration transistor-resistor array to result in a comparing voltage across the calibration transistor-resistor array. The resistance of the calibration transistor-resistor array is determined according to a digital code generated from the digital code generator. The voltage level outputted from the comparator is changed from a first state to a second state when the digital code generator up counts to a target digital code such that the comparing voltage is just greater than the reference voltage. The decision and latch circuit records the target digital code into therein. The resistance of the termination resistor is adjustable according to the target digital code.
    Type: Application
    Filed: August 18, 2006
    Publication date: February 22, 2007
    Applicant: Via Technologies, Inc.
    Inventors: Joanna Lin, Lester Yeh