Abstract: The invention discloses an interface system for an interconnected die and an MPU and a communication method thereof. The system comprises a data interface, an interrupt interface, and a debugging interface; the data interface comprises an SPI interface, a DDR data interface, and a DMA control interface; the interrupt interface is used for receiving an interrupt data packet from the network and parsing the interrupt data packet to obtain a pulse interrupt input required by the MPU; the debugging interface comprises a JTAG-Core debugging interface, which is used for receiving a debugging data packet from the network and translating the debugging data packet into a JTAG protocol for MPU debugging. The invention realizes the expansion of the master device MPU in the high-performance information processing microsystem and the high-speed communication between the master device and the interconnected dies.

Abstract: The present disclosure relates to an on-chip network design method for a distributed parallel operation algorithm. According to a distributed parallel operation algorithm of an on-chip network, the on-chip network is divided into two layers, including a unicast network and a multicast network, where the unicast network is configured to implement point-to-point propagation between nodes and transmit independent operation data required by operation nodes to each operation node in a form of unicast; and the multicast network is a customized multicast network for the distributed parallel operation algorithm and configured to transmit common operation data to all the operation nodes, such that a data packet in the network is efficiently transmitted through a combination of the unicast network and the multicast network. By designing a multicast tree transmission architecture for the distributed parallel operation algorithm, a bidirectional replication node or a receiving node is disposed in each operation node.

Abstract: The invention discloses connections among dies, in particular to interconnected dies, comprising: protocol conversion circuits, external interconnected interfaces and networks on die. The protocol conversion circuits comprise multiple protocol conversion modules which are used to communicate with various standard mainstream protocol interfaces. The external interconnected interfaces comprise several synchronization controllers which are used to communicate with other interconnected dies. The networks on die comprise transmission buses and routers which are used to transmit data packets from the interfaces or other interconnected dies. At the same time, the synchronization controllers and the protocol conversion modules are respectively connected with boundary nodes of the networks on die.

Abstract: The invention relates to a data transmission method, in particular to a data transmission event used for interconnected dies, comprising read events, write events and interrupt events; the read event comprises read request events and read response events; the write event comprises write data events and write response events; the write data event and the read request event are both sent by the master device and received by the slave device; the writing response event and the read response event are both sent by the slave device and received by the master device.

Abstract: The invention discloses clock management of chips, in particular to the clock domain system of interconnected dies and its management methods. The clock domain systems of the interconnected dies, comprising: global clock domains used to manage interior networks on die of the interconnected dies, standard protocol interface clock domains used to manage standard protocol conversion modules and interface source synchronous clock domains used to manage expansion synchronization controllers across dies. The clock domain systems of the interconnected dies provided by the invention modularize complicated clock networks by isolating each module from the perspective of clocks and simultaneously initiate clock synchronization among all clock domains, which is easy for interconnected network setups.

Abstract: The invention discloses an interface system for an interconnected die and an MPU and a communication method thereof. The system comprises a data interface, an interrupt interface, and a debugging interface; the data interface comprises an SPI interface, a DDR data interface, and a DMA control interface; the interrupt interface is used for receiving an interrupt data packet from the network and parsing the interrupt data packet to obtain a pulse interrupt input required by the MPU; the debugging interface comprises a JTAG-Core debugging interface, which is used for receiving a debugging data packet from the network and translating the debugging data packet into a JTAG protocol for MPU debugging. The invention realizes the expansion of the master device MPU in the high-performance information processing microsystem and the high-speed communication between the master device and the interconnected dies.

Abstract: The invention relates to a communication method and its system between interconnected die and DSP/FPGA. The method includes multiple data interfaces. Each data interface is provided with a different protocol conversion module, wherein the data interface communication includes data input conversion and data output conversion; wherein during input conversion, the external data is converted into a unified data protocol format by protocol conversion module, which is transmitted to the network on die for unified data transmission; wherein during output conversion, the internal data is converted into different data protocol formats by protocol conversion module, and then enters different data interfaces and is transmitted to the DSP/FPGA. This method allows each device and component to be connected to the multi-die system in any form, which improves the flexibility of the system.

Abstract: The invention relates to an inter-die high-speed expansion system and an expansion method thereof. The high speed expansion system comprises a cross-die expansion synchronizer and a direct-connection path connected with the expansion synchronizer, the cross-die expansion synchronizer is arranged on dies, the dies are connected through the cross-die expansion synchronizer and the direct-connection path, the cross-die expansion synchronizer is used for controlling data transmission, the data comprises a clock signal, a reset signal, a handshake signal and a data signal, and all the signals appear in pairs in a differential form. The system has good universality and low complexity, can realize the flexible expansion of interconnected dies, and can form a larger package level network, which lays a foundation for subsequent microsystem integration.