Abstract: Integrated circuit dies are prepared for imaging by completely etching away all metal from the metal lines without removing barrier layers that underlie the metal lines. The metal vias may also be removed, especially if they are formed from the same metal as the metal lines, as in copper damascene circuits. This provides high contrast images that permits circuit layout extraction software to readily distinguish between metal lines and vias.

Abstract: Integrated circuit dies are prepared for imaging by completely etching away all metal from the metal lines without removing barrier layers that underlie the metal lines. The metal vias may also be removed, especially if they are formed from the same metal as the metal lines, as in copper damascene circuits. This provides high contrast images that permits circuit layout extraction software to readily distinguish between metal lines and vias.

Abstract: A system and method for aligning tile images of an area of interest of an integrated circuit having N metal layers M, where N>1, includes a parametric representation algorithm for extracting parametric representations of edges from an image showing metal layer (MN) and at least a proportion of metal layer (MN?1) of the integrated circuit to produce a parametric representation of the edges visible on the respective metal layers. The parametric representations include an indication of the metal layer with which each extracted edge is associated and at least one of x and y coordinates associated with each of the extracted edges.