Abstract: A binary tree-like structure for converting bit rates in a telecommunication system, comprising at least one cyclic generator (CG) adapted to present a higher bit rate called R1 substantially as a sum of two lower bit rates called R2 and R3 by cyclically producing, per n clocks of the bit rate R1, m first type signals as clocks of the bit rate R2 and (n?m) second type signals as clocks of the bit rate R3, where m and n are parameters of the CG and integers such, that m<n. The two lower bit rates R2 and R3, based on its parameters m and n, can be presented as follows: R2=mR1/n, R3=(n?m)R1/n. The higher bit rate R1 of a particular CG is either obtained from outside of the binary tree-like structure or constitutes a lower bit rate of another, upper range CG of the structure, while each of the lower bit rates R2 or R3 of a particular CG is either dispatched away from the structure or constitutes a higher bit rate of another, lower range CG of the structure.

Abstract: A method and a generator are described for high speed generation of an S-bit long pattern of a PRBS sequence to be periodically burst on to a bus of width S. The technique provides the calculation time being independent from the width S of the bus, and comprises calculation of all S bits of the PRBS pattern separately and in parallel by using previous PRBS patterns stored in a memory. For each bit to be generated, the generator performs a constant number N of logical operations require(by a polynomial defining the PRBS sequence.

Abstract: The invention discloses a cyclic generator of enabling/disabling signals (EG) adapted to convert an incoming data stream having a bit rate RI into an outgoing data stream having a bit rate R2, wherein R1≅mR2/n , m<n, m and n—integers being parameters of said EG selected to provide m enable signals per n clocks of the bit rate R2, wherein the EG is characterized by having a number of internal states <n and being capable of generating periodic enabling/disabling output signals such that the disable signals are optimally distributed among the enable signals.

Abstract: A method and a generator are described for high speed generation of an S-bit long pattern of a PRBS sequence to be periodically burst on to a bus of width S. The technique provides the calculation time being independent from the width S of the bus, and comprises calculation of all S bits of the PRBS pattern separately and in parallel by using previous PRBS patterns stored in a memory. For each bit to be generated, the generator performs a constant number N of logical operations required (by a polynomial defining the PRBS sequence.