Patents by Inventor Lev Makovsky
Lev Makovsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11385704Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.Type: GrantFiled: February 24, 2021Date of Patent: July 12, 2022Assignee: Intel CorporationInventors: Alexander Gendler, Igor Yanover, Gavri Berger, Edo Hachamo, Elkana Korem, Hanan Shomroni, Daniela Kaufman, Lev Makovsky, Haim Granot
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Publication number: 20210271305Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.Type: ApplicationFiled: February 24, 2021Publication date: September 2, 2021Inventors: Alexander Gendler, Igor Yanover, Gavri Berger, Edo Hachamo, Elkana Korem, Hanan Shomroni, Daniela Kaufman, Lev Makovsky, Haim Granot
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Patent number: 11106271Abstract: In one embodiment, a processor core has one or more execution units, a first memory array having a first protection circuit to provide soft error protection to the first memory array, and a control circuit. A power controller coupled to the core may include a protection control circuit, in response to an update to an operating voltage to be provided to the core, to cause the core to disable the first protection circuit. Other embodiments are described and claimed.Type: GrantFiled: September 17, 2019Date of Patent: August 31, 2021Assignee: Intel CorporationInventors: Alexander Gendler, Arkady Bramnik, Lev Makovsky
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Patent number: 10936041Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.Type: GrantFiled: March 29, 2019Date of Patent: March 2, 2021Assignee: Intel CorporationInventors: Alexander Gendler, Igor Yanover, Gavri Berger, Edo Hachamo, Elkana Korem, Hanan Shomroni, Daniela Kaufman, Lev Makovsky, Haim Granot
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Publication number: 20200310511Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.Type: ApplicationFiled: March 29, 2019Publication date: October 1, 2020Inventors: Alexander Gendler, Igor Yanover, Gavri Berger, Edo Hachamo, Elkana Korem, Hanan Shomroni, Daniela Kaufman, Lev Makovsky, Haim Granot
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Patent number: 10691850Abstract: A power analysis system for an integrated circuit device design can use machine learning to determine an estimated power consumption of the design. In various examples, the system can generate workloads for a power projection tool, which can include less than all the data of a full suite of power projection tests. The results from the power projection tool can be used to train a machine learning data model. From the results, the data model can learn the functions of the design by grouping together cells that are triggered together by the same signals. The data model can also learn estimated power consumption for each of the functions. The output of the data model can then be used to configure a design testing tool, which can run tests on the design. The output of the tests can then be used to compute an estimated overall power consumption for the design.Type: GrantFiled: December 13, 2018Date of Patent: June 23, 2020Assignee: Amazon Technologies, Inc.Inventors: Lev Makovsky, Adi Habusha, Ron Diamant
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Publication number: 20200012333Abstract: In one embodiment, a processor core has one or more execution units, a first memory array having a first protection circuit to provide soft error protection to the first memory array, and a control circuit. A power controller coupled to the core may include a protection control circuit, in response to an update to an operating voltage to be provided to the core, to cause the core to disable the first protection circuit. Other embodiments are described and claimed.Type: ApplicationFiled: September 17, 2019Publication date: January 9, 2020Inventors: Alexander Gendler, Arkady Bramnik, Lev Makovsky
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Patent number: 10467011Abstract: A processor of an aspect includes a decode unit to decode a thread pause instruction from a first thread. A back-end portion of the processor is coupled with the decode unit. The back-end portion of the processor, in response to the thread pause instruction, is to pause processing of subsequent instructions of the first thread for execution. The subsequent instructions occur after the thread pause instruction in program order. The back-end portion, in response to the thread pause instruction, is also to keep at least a majority of the back-end portion of the processor, empty of instructions of the first thread, except for the thread pause instruction, for a predetermined period of time. The majority may include a plurality of execution units and an instruction queue unit.Type: GrantFiled: July 21, 2014Date of Patent: November 5, 2019Assignee: Intel CorporationInventors: Lihu Rappoport, Zeev Sperber, Michael Mishaeli, Stanislav Shwartsman, Lev Makovsky, Adi Yoaz, Ofer Levy
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Patent number: 10437315Abstract: In one embodiment, a processor core has one or more execution units, a first memory array having a first protection circuit to provide soft error protection to the first memory array, and a control circuit. A power controller coupled to the core may include a protection control circuit, in response to an update to an operating voltage to be provided to the core, to cause the core to disable the first protection circuit. Other embodiments are described and claimed.Type: GrantFiled: June 22, 2017Date of Patent: October 8, 2019Assignee: Intel CorporationInventors: Alexander Gendler, Arkady Bramnik, Lev Makovsky
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Publication number: 20180373315Abstract: In one embodiment, a processor core has one or more execution units, a first memory array having a first protection circuit to provide soft error protection to the first memory array, and a control circuit. A power controller coupled to the core may include a protection control circuit, in response to an update to an operating voltage to be provided to the core, to cause the core to disable the first protection circuit. Other embodiments are described and claimed.Type: ApplicationFiled: June 22, 2017Publication date: December 27, 2018Inventors: Alexander Gendler, Arkady Bramnik, Lev Makovsky
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Publication number: 20180173298Abstract: An apparatus is provided, comprising: a first circuitry configured to generate a signal at a voltage level for one or more components; a second circuitry configured to generate a clock at a frequency level for the one or more components; a third circuitry configured to intermittently measure a current level of the signal; a fourth circuitry configured to estimate a first average of the current level of the signal over a first time-window; and a fifth circuitry configured to, in response to the first average being higher than a threshold average current, facilitate regulating one or both the voltage level of the signal or the frequency level of the clock.Type: ApplicationFiled: December 16, 2016Publication date: June 21, 2018Applicant: Intel CorporationInventors: Alexander Gendler, Boris Mishori, Krishnakanth V. Sistla, Ankush Varma, Avinash N. Ananthakrishnan, Lev Makovsky, Michael Zelikson, Eran Altshuler, Israel Stolero
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Patent number: 9471088Abstract: In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed.Type: GrantFiled: June 25, 2013Date of Patent: October 18, 2016Assignee: Intel CorporationInventors: Alexander Gendler, Efraim Rotem, Julius Mandelblat, Alexander Lyakhov, Larisa Novakovsky, George Leifman, Lev Makovsky, Ariel Sabba, Niv Tokman
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Patent number: 9292362Abstract: In an embodiment, a processor includes at least a first core. The first core includes execution logic to execute operations, and a first event counter to determine a first event count associated with events of a first type that have occurred since a start of a first defined interval. The first core also includes a second event counter to determine a second event count associated with events of a second type that have occurred since the start of the first defined interval, and stall logic to stall execution of operations including at least first operations associated with events of the first type, until the first defined interval is expired responsive to the first event count exceeding a first combination threshold concurrently with the second event count exceeding a second combination threshold. Other embodiments are described and claimed.Type: GrantFiled: June 25, 2013Date of Patent: March 22, 2016Assignee: Intel CorporationInventors: Lev Makovsky, Zeev Sperber, Efraim Rotem, Nir Rosenzweig, Stanislav Shwartsman, Raanan Sade, Igor Yanover, Gavri Berger, Tomer Weiner, Ron Gabor
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Publication number: 20160019063Abstract: A processor of an aspect includes a decode unit to decode a thread pause instruction from a first thread. A back-end portion of the processor is coupled with the decode unit. The back-end portion of the processor, in response to the thread pause instruction, is to pause processing of subsequent instructions of the first thread for execution. The subsequent instructions occur after the thread pause instruction in program order. The back-end portion, in response to the thread pause instruction, is also to keep at least a majority of the back-end portion of the processor, empty of instructions of the first thread, except for the thread pause instruction, for a predetermined period of time. The majority may include a plurality of execution units and an instruction queue unit.Type: ApplicationFiled: July 21, 2014Publication date: January 21, 2016Applicant: Intel CorporationInventors: Lihu Rappoport, Zeev Sperber, Michael Mishaeli, Stanislav Shwartsman, Lev Makovsky, Adi Yoaz, Ofer Levy
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Publication number: 20140380338Abstract: In an embodiment, a processor includes at least a first core. The first core includes execution logic to execute operations, and a first event counter to determine a first event count associated with events of a first type that have occurred since a start of a first defined interval. The first core also includes a second event counter to determine a second event count associated with events of a second type that have occurred since the start of the first defined interval, and stall logic to stall execution of operations including at least first operations associated with events of the first type, until the first defined interval is expired responsive to the first event count exceeding a first combination threshold concurrently with the second event count exceeding a second combination threshold. Other embodiments are described and claimed.Type: ApplicationFiled: June 25, 2013Publication date: December 25, 2014Inventors: LEV MAKOVSKY, ZEEV SPERBER, EFRAIM ROTEM, NIR ROSENZWEIG, STANISLAV SHWARTSMAN, RAANAN SADE, IGOR YANOVER, GAVRI BERGER, TOMER WEINER, RON GABOR
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Publication number: 20140380081Abstract: In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed.Type: ApplicationFiled: June 25, 2013Publication date: December 25, 2014Inventors: Alexander Gendler, Efraim Rotem, Julius Mandelblat, Alexander Lyakhov, Larisa Novakovsky, George Leifman, Lev Makovsky, Ariel Sabba, Niv Tokman