Abstract: A dual/triple redundant computer system having in one of the preferred embodiments triple redundant I/O modules and dual redundant central processor modules (CPM) that operate in parallel executing the same application program. Each input module includes three input circuits operating in parallel. The first CPM receives input data from first and third input circuits and transmits input data of the first input circuit to the second CPM. The second CPM receives input data from second and third input circuits and transmits input data of the second input circuit to the first CPM. Each CPM then performs a two-out-of-two vote among input data produced by first, second, and third input circuits and utilizes an outvoted data as input to the application program to provide output data by execution of the application program. Each output module includes three microcontrollers operating in parallel.