Abstract: An electrical power switch, the power switch comprising: a pair of substantially parallel half bridges; a printed circuit board (PCB) controller operable to turn ON and turn OFF the half bridges; power terminals for coupling a high energy power source to the half bridges; a power phase output terminal for connecting a load to the half bridges; wherein the half bridges, PCB, power terminals, and power phase output terminal, are encapsulated in a same encapsulation envelope having a relatively large planar first face surface on which contact surfaces of the terminals are exposed.

Abstract: An electrical power switch, the power switch comprising: a pair of substantially parallel half bridges; a printed circuit board (PCB) controller operable to turn ON and turn OFF the half bridges; power terminals for coupling a high energy power source to the half bridges; a power phase output terminal for connecting a load to the half bridges; wherein the half bridges, PCB, power terminals, and power phase output terminal, are encapsulated in a same encapsulation envelope having a relatively large planar first face surface on which contact surfaces of the terminals are exposed.

Abstract: An electrical power switch, the power switch comprising: an array of rows and columns of lateral field effect (LFET) transistors, each transistor having a source, drain, and gate; a plurality of internal interconnect layers comprising metallizations configured to connect the transistors to operate in parallel; a source electrode and a drain electrode for respectively connecting the sources and drains of the transistors to an external circuit; and a bridging interconnect layer comprising: a plurality of undulating source bridging conductors that provide electrical connections for the sources of the transistors to the source electrode; and a plurality of undulating drain bridging conductors that provide electrical connections for the drains of the transistors to the drain electrode.

Abstract: An apparatus includes a circuitry to perform a high current and/or a high voltage switching. The circuitry includes a first Gallium Nitride (GaN) on a silicon (Si) substrate lateral field effect transistor. A source terminal of the first GaN lateral field effect transistor on the Si substrate includes an electrical connection to backside of P-type Si substrate through a high voltage isolated resistor that is coupled to a source terminal or a second resistor that is operably coupled to a drain terminal and a substrate terminal. The high voltage isolated resistor and the second resistor cause to a leakage current from the drain terminal to the source terminal via a buffer layer. The leakage current equalizes the voltage drop on the first GaN lateral field effect transistor on the Si substrate to a voltage drop on a serially connected second GaN lateral field effect transistor on the Si substrate.

Abstract: An apparatus includes a circuitry to perform a high current and/or a high voltage switching. The circuitry includes a first Gallium Nitride (GaN) on a silicon (Si) substrate lateral field effect transistor. A source terminal of the first GaN lateral field effect transistor on the Si substrate includes an electrical connection to backside of P-type Si substrate through a high voltage isolated resistor that is coupled to a source terminal or a second resistor that is operably coupled to a drain terminal and a substrate terminal. The high voltage isolated resistor and the second resistor cause to a leakage current from the drain terminal to the source terminal via a buffer layer. The leakage current equalizes the voltage drop on the first GaN lateral field effect transistor on the Si substrate to a voltage drop on a serially connected second GaN lateral field effect transistor on the Si substrate.

Abstract: An embodiment of the invention relates to a semiconductor device comprising: first and second electrodes comprising first and second busbars respectively that decrease in cross section in opposite directions; and a plurality of interleaving first and second conducting fingers that extend from the first and second busbars respectively.

Abstract: An embodiment of the invention relates to a semiconductor device comprising: first and second electrodes comprising first and second busbars respectively that decrease in cross section in opposite directions; and a plurality of interleaving first and second conducting fingers that extend from the first and second busbars respectively.