Abstract: A system and method that tests an IP component of a hardware design generates an abstract model of the IP component based on knowledge of the design and one or more protocols implemented with the IP component. A generic driver and associated interfaces are additionally generated or selected to test the IP component within the hardware design.

Abstract: A method and apparatus for modeling using a hardware-software software co-verification environment is provided. An instruction set simulator is coupled to a simulator circuit to determine if the hardware design is correct. Specifically, the instruction set simulator acts as a “master” to the simulator circuit, thus providing a faster simulation environment. The simulator circuit contains a bus functional model, a hardware model, transfer memory, and the hardware design to be tested. The hardware model is designed to emulate a micro-controller. By disabling a processor within the hardware model, the speed of the simulation is restricted only by the speed of the instruction set simulator or the hardware design. Furthermore, the hardware design may be uncoupled from the simulator circuit in order to initialize the operating system.