Patents by Inventor Levon MSRYAN

Levon MSRYAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DDR PHY power collapse circuit for multimode double data rate synchronous dynamic random access memory
    Patent number: 12211578
    Abstract: A transmitter circuit includes a first driver circuit configured to drive an input/output pad in an integrated circuit device, the first driver circuit including a thin-oxide transistor configured to couple the input/output pad to a first voltage rail when the transmitter circuit is operated in a first mode; a gate pullup transistor configured to couple a gate of the thin-oxide transistor to a second voltage rail when voltage of a third voltage rail is collapsed to a zero-volt level; and a switch configured to block transmission of a gating signal to the gate of the thin-oxide transistor when the voltage of the third voltage rail is collapsed to the zero-volt level.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: January 28, 2025
    Assignee: QUALCOMM INCORPORATED
    Inventors: Levon Msryan, Tigran Melikyan, Ashwin Sethuram, Satish Krishnamoorthy
  • DDR PHY POWER COLLAPSE CIRCUIT FOR MULTIMODE DOUBLE DATA RATE SYNCHRONOUS DYNAMIC RANDOM ACCESS
    Publication number: 20240144980
    Abstract: A transmitter circuit includes a first driver circuit configured to drive an input/output pad in an integrated circuit device, the first driver circuit including a thin-oxide transistor configured to couple the input/output pad to a first voltage rail when the transmitter circuit is operated in a first mode; a gate pullup transistor configured to couple a gate of the thin-oxide transistor to a second voltage rail when voltage of a third voltage rail is collapsed to a zero-volt level; and a switch configured to block transmission of a gating signal to the gate of the thin-oxide transistor when the voltage of the third voltage rail is collapsed to the zero-volt level.
    Type: Application
    Filed: October 26, 2022
    Publication date: May 2, 2024
    Inventors: Levon MSRYAN, Tigran MELIKYAN, Ashwin SETHURAM, Satish KRISHNAMOORTHY