Patents by Inventor Lewis A. Binns
Lewis A. Binns has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8339605Abstract: A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.Type: GrantFiled: November 30, 2010Date of Patent: December 25, 2012Assignees: International Business Machines Corporation, Nanometrics IncorporatedInventors: Christopher P. Ausschnitt, Lewis A. Binns, Jaime D. Morillo, Nigel P. Smith
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Patent number: 8107079Abstract: A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.Type: GrantFiled: November 9, 2010Date of Patent: January 31, 2012Assignees: International Business Machines Corporation, Nanometrics IncorporatedInventors: Christopher P. Ausschnitt, Lewis A. Binns, Jaime D. Morillo, Nigel P. Smith
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Publication number: 20110069314Abstract: A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.Type: ApplicationFiled: November 30, 2010Publication date: March 24, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher P. Ausschnitt, Lewis A. Binns, Jaime D. Morillo, Nigel P. Smith
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Publication number: 20110058170Abstract: A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.Type: ApplicationFiled: November 9, 2010Publication date: March 10, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher P. Ausschnitt, Lewis A. Binns, Jaime D. Morillo, Nigel P. Smith
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Patent number: 7876439Abstract: A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.Type: GrantFiled: June 23, 2008Date of Patent: January 25, 2011Assignee: International Business Machines CorporationInventors: Christopher P. Ausschnitt, Lewis A. Binns, Jaime D. Morillo, Nigel P. Smith
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Patent number: 7473502Abstract: A method of determining and correcting for distortions introduced by an imaging tool. The method includes providing an imaging tool having a field of view (FOV), and creating a target pattern containing a regular array of symmetric sub-patterns having locations spanning the FOV. Using the imaging tool, the method then includes measuring relative position of the sub-pattern images at one or more target orientations, determining tool-induced sub-pattern position deviations from designed locations of the sub-patterns, and applying corrections to compensate for an orientation independent component of the sub-pattern position deviations. The target pattern may be mounted on a stage of the measurement tool, created on a mask used in the lithographic process, or created on a wafer being measured by the measuring tool.Type: GrantFiled: August 3, 2007Date of Patent: January 6, 2009Assignees: International Business Machines Corporation, Nanometrics IncorporatedInventors: Chistopher P. Ausschnitt, Lewis A. Binns, Jennifer L. Morningstar, Nigel Smith
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Patent number: 7474401Abstract: A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.Type: GrantFiled: September 13, 2005Date of Patent: January 6, 2009Assignees: International Business Machines Corporation, Accent Optical TechnologiesInventors: Christopher P. Ausschnitt, Lewis A. Binns, Jaime D. Morillo, Nigel P. Smith
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Publication number: 20080259334Abstract: A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.Type: ApplicationFiled: June 23, 2008Publication date: October 23, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher P. Ausschnitt, Lewis A. Binns, Jaime D. Morillo, Nigel P. Smith
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Publication number: 20070058169Abstract: A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.Type: ApplicationFiled: September 13, 2005Publication date: March 15, 2007Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, ACCENT OPTICAL TECHNOLOGIES, INC.Inventors: Christopher Ausschnitt, Lewis Binns, Jaime Morillo, Nigel Smith