Patents by Inventor Lewis F. Lahr

Lewis F. Lahr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10884972
    Abstract: Disclosed herein are systems and techniques for serial peripheral interface (SPI) functionality for node transceivers in a two-wire communication bus. For example, in some embodiments, a node transceiver may include SPI circuitry and upstream or downstream transceiver circuitry. SPI commands received via the SPI circuitry may be executed by the node transceiver, or transmitted upstream or downstream along the two-wire bus for execution by another node transceiver or a slave device coupled to another node transceiver.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: January 5, 2021
    Assignee: Analog Devices, Inc.
    Inventors: Martin Kessler, Lewis F. Lahr, William Hooper
  • Patent number: 10872049
    Abstract: Disclosed herein are systems and techniques for general purpose input/output (GPIO)-to-GPIO communication in a multi-node, daisy-chained network. In some embodiments, a transceiver may support GPIO between multiple nodes, without host intervention after initial programming. In some such embodiments, the host may be required only for initial setup of the virtual ports. In some embodiments, GPIO pins can be inputs (which may change virtual ports) or outputs (which may reflect virtual ports). In some embodiments, multiple virtual ports may be mapped to one GPIO output pin (with the values OR'ed together, for example). In some embodiments, multiple GPIO input pins may be mapped to one virtual port. For example, multiple GPIO input pin values may be OR'ed together, even if they come from multiple nodes.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: December 22, 2020
    Assignee: ANALOG DEVICES, INC.
    Inventors: Martin Kessler, William Hooper, Lewis F. Lahr
  • Publication number: 20200356521
    Abstract: Disclosed herein are systems and techniques for serial peripheral interface (SPI) functionality for node transceivers in a two-wire communication bus. For example, in some embodiments, a node transceiver may include SPI circuitry and upstream or downstream transceiver circuitry. SPI commands received via the SPI circuitry may be executed by the node transceiver, or transmitted upstream or downstream along the two-wire bus for execution by another node transceiver or a slave device coupled to another node transceiver.
    Type: Application
    Filed: May 8, 2019
    Publication date: November 12, 2020
    Applicant: Analog Devices, Inc.
    Inventors: Martin KESSLER, Lewis F. LAHR, William HOOPER
  • Publication number: 20200257646
    Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Applicant: Analog Devices, Inc.
    Inventors: Martin KESSLER, Miguel A. CHAVEZ, Lewis F. LAHR, William HOOPER, Robert Adams, Peter SEALEY
  • Patent number: 10649948
    Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: May 12, 2020
    Assignee: ANALOG DEVICES, INC.
    Inventors: Martin Kessler, Miguel Chavez, Lewis F. Lahr, William Hooper, Robert Adams, Peter Sealey
  • Publication number: 20190278733
    Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.
    Type: Application
    Filed: May 30, 2019
    Publication date: September 12, 2019
    Applicant: Analog Devices, Inc.
    Inventors: Martin KESSLER, Miguel CHAVEZ, Lewis F. LAHR, William HOOPER, Robert Adams, Peter SEALEY
  • Patent number: 10397021
    Abstract: Disclosed herein are systems and techniques for slave-to-slave communication in a multi-node, daisy-chained network. Slave nodes may provide or receive upstream or downstream data directly to/from other slave nodes, without the need for data slots first to route through the master node.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: August 27, 2019
    Assignee: Analog Devices, Inc.
    Inventors: Martin Kessler, William Hooper, Lewis F. Lahr
  • Patent number: 10311010
    Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: June 4, 2019
    Assignee: ANALOG DEVICES, INC.
    Inventors: Martin Kessler, Miguel Chavez, Lewis F. Lahr, William Hooper, Robert Adams, Peter Sealey
  • Patent number: 10250376
    Abstract: Disclosed herein are systems and methods for clock sustain in a two-wire communication systems and applications thereof. In some embodiments, in a clock sustain state, slave nodes with processors and digital to analog converters (DACs) may be powered down efficiently in the event of lost bus communication. For example, when the bus loses communication and a reliable clock cannot be recovered by the slave node, the slave node may enter the sustain state and, if enabled, signals this event to a general purpose input/output (GPIO) pin. In the clock sustain state, the slave node phase lock loop (PLL) may continue to run for a predetermined number of SYNC periods, while attenuating the inter-integrated circuit transmit (I2S DTXn) data from its current value to 0. After the predetermined number of SYNC periods, the slave node may reset and reenter a power-up state.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: April 2, 2019
    Assignee: ANALOG DEVICES, INC.
    Inventors: William Hooper, Lewis F. Lahr
  • Publication number: 20170222790
    Abstract: Disclosed herein are systems and methods for clock sustain in a two-wire communication systems and applications thereof. In some embodiments, in a clock sustain state, slave nodes with processors and digital to analog converters (DACs) may be powered down efficiently in the event of lost bus communication. For example, when the bus loses communication and a reliable clock cannot be recovered by the slave node, the slave node may enter the sustain state and, if enabled, signals this event to a general purpose input/output (GPIO) pin. In the clock sustain state, the slave node phase lock loop (PLL) may continue to run for a predetermined number of SYNC periods, while attenuating the inter-integrated circuit transmit (I2S DTXn) data from its current value to 0. After the predetermined number of SYNC periods, the slave node may reset and reenter a power-up state.
    Type: Application
    Filed: January 20, 2017
    Publication date: August 3, 2017
    Applicant: Analog Devices, Inc.
    Inventors: WILLIAM HOOPER, Lewis F. LAHR
  • Publication number: 20170222829
    Abstract: Disclosed herein are systems and techniques for slave-to-slave communication in a multi-node, daisy-chained network. Slave nodes may provide or receive upstream or downstream data directly to/from other slave nodes, without the need for data slots first to route through the master node.
    Type: Application
    Filed: January 20, 2017
    Publication date: August 3, 2017
    Applicant: Analog Devices, Inc.
    Inventors: Martin Kessler, William Hooper, Lewis F. Lahr
  • Publication number: 20170220502
    Abstract: Disclosed herein are systems and techniques for general purpose input/output (GPIO)-to-GPIO communication in a multi-node, daisy-chained network. In some embodiments, a transceiver may support GPIO between multiple nodes, without host intervention after initial programming. In some such embodiments, the host may be required only for initial setup of the virtual ports. In some embodiments, GPIO pins can be inputs (which may change virtual ports) or outputs (which may reflect virtual ports). In some embodiments, multiple virtual ports may be mapped to one GPIO output pin (with the values OR'ed together, for example). In some embodiments, multiple GPIO input pins may be mapped to one virtual port. For example, multiple GPIO input pin values may be OR'ed together, even if they come from multiple nodes.
    Type: Application
    Filed: January 20, 2017
    Publication date: August 3, 2017
    Applicant: Analog Devices, Inc.
    Inventors: Martin KESSLER, William HOOPER, Lewis F. LAHR
  • Publication number: 20160350240
    Abstract: A serial peripheral interface (SPI) host port is disclosed that enables a host external to a processor to access the processor's memory-mapped resources using SPI memory command protocol. An exemplary processor can include a system interconnect connected to memory-mapped resources and a SPI host port connected to the system interconnect. The SPI host port is configured to use SPI memory command protocol to access memory-mapped resources of the processor for the host external to the processor.
    Type: Application
    Filed: May 29, 2015
    Publication date: December 1, 2016
    Applicant: ANALOG DEVICES GLOBAL
    Inventors: Richard F. Grafton, Shivakumar Patil, James Potts, Lewis F. Lahr
  • Patent number: 9448959
    Abstract: In an example embodiment, a two-wire communication protocol engine manages control and data transmissions in a bi-directional, multi-node bus system where each node is connected over a twisted wire pair bus to another node. Some embodiments include a state machine that allows for synchronized updates of configuration data across the system, a distributed interrupt system, a synchronization pattern based on data coding used in the system, and data scrambling applied to a portion of the data transmitted over the twisted wire pair bus. The multi-node bus system comprises a master node and a plurality of slave nodes. The slave nodes can be powered over the twisted wire pair bus.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: September 20, 2016
    Assignee: ANALOG DEVICES, INC.
    Inventors: William Hooper, Martin Kessler, Lewis F. Lahr, Michael Giancioppo
  • Publication number: 20160041941
    Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.
    Type: Application
    Filed: October 16, 2015
    Publication date: February 11, 2016
    Applicant: ANALOG DEVICES, INC.
    Inventors: MARTIN KESSLER, MIGUEL CHAVEZ, LEWIS F. LAHR, WILLIAM HOOPER, ROBERT ADAMS, PETER SEALEY
  • Patent number: 9197226
    Abstract: According to one example, a digital phase detector is disclosed for use with a phase lock loop. The digital phase detector is configured to operate in a low-frequency environment and to filter noise and transients in a signal, while also being tolerant of dropped phase pulses. In some embodiments, the digital phase detector is configured to measure up to two REFCLK edges with respect to a FBCLK signal, and if an edge occurs in the first half of REFCLK, classify the edge as lagging, and if an edge occurs in the second half of REFCLK, classify the edge as leading. If both edges are leading or both are lagging, the smaller of the two is used as the phase. If one is leading and one is lagging, the difference is used as the phase.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: November 24, 2015
    Assignee: Analog Devices, Inc.
    Inventor: Lewis F. Lahr
  • Patent number: 9059724
    Abstract: In an example embodiment, a signal processor is disclosed that is configured to decode a clock-first, change-on-zero differential Manchester encoded data stream. The data stream has no local clock, and both combinatorial and sequential logic is used to decode the stream into a clocked data signal and an optional error signal. Decoding comprises a parser that separates the input data stream into an intermediate data signal, an intermediate clock signal, and a conditioning signal. A data and error generator receives the three signals and outputs a clocked data signal and a clocked error signal.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: June 16, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Lewis F. Lahr, William J. Thomas, William Hooper
  • Publication number: 20150009050
    Abstract: In an example embodiment, a signal processor is disclosed that is configured to decode a clock-first, change-on-zero differential Manchester encoded data stream. The data stream has no local clock, and both combinatorial and sequential logic is used to decode the stream into a clocked data signal and an optional error signal. Decoding comprises a parser that separates the input data stream into an intermediate data signal, an intermediate clock signal, and a conditioning signal. A data and error generator receives the three signals and outputs a clocked data signal and a clocked error signal.
    Type: Application
    Filed: February 27, 2014
    Publication date: January 8, 2015
    Applicant: ANALOG DEVICES, INC.
    Inventors: Lewis F. Lahr, William J. Thomas, William Hooper
  • Publication number: 20150008960
    Abstract: According to one example, a digital phase detector is disclosed for use with a phase lock loop. The digital phase detector is configured to operate in a low-frequency environment and to filter noise and transients in a signal, while also being tolerant of dropped phase pulses. In some embodiments, the digital phase detector is configured to measure up to two REFCLK edges with respect to a FBCLK signal, and if an edge occurs in the first half of REFCLK, classify the edge as lagging, and if an edge occurs in the second half of REFCLK, classify the edge as leading. If both edges are leading or both are lagging, the smaller of the two is used as the phase. If one is leading and one is lagging, the difference is used as the phase.
    Type: Application
    Filed: December 18, 2013
    Publication date: January 8, 2015
    Applicant: Analog Devices, Inc.
    Inventor: Lewis F. Lahr
  • Publication number: 20140101351
    Abstract: In an example embodiment, a two-wire communication protocol engine manages control and data transmissions in a bi-directional, multi-node bus system where each node is connected over a twisted wire pair bus to another node. Some embodiments include a state machine that allows for synchronized updates of configuration data across the system, a distributed interrupt system, a synchronization pattern based on data coding used in the system, and data scrambling applied to a portion of the data transmitted over the twisted wire pair bus. The multi-node bus system comprises a master node and a plurality of slave nodes. The slave nodes can be powered over the twisted wire pair bus.
    Type: Application
    Filed: October 25, 2013
    Publication date: April 10, 2014
    Applicant: ANALOG DEVICES, INC.
    Inventors: William Hooper, Martin Kessler, Lewis F. Lahr, Michael Giancioppo