Patents by Inventor Lewis Kootstra

Lewis Kootstra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060242338
    Abstract: Network devices, systems, and methods are provided involving item routing management. One embodiment includes a computing device item routing management having a number of queues and a logic component. The number of queues can hold a number of items to be routed, via a routing path within the computing device, at least one of the items having time information associated therewith. The logic component can review at least one of the number of items held within the queue based upon the time information to determine whether to discard the item.
    Type: Application
    Filed: April 26, 2005
    Publication date: October 26, 2006
    Inventors: Lewis Kootstra, Michael Vacanti
  • Publication number: 20060230195
    Abstract: Devices, systems, and methods are provided involving queue management. One embodiment includes a computing device having a priority aware queue. In this embodiment, the device includes a queue having a number of counters associated therewith to monitor a number of items each having a classification level associated therewith. The device also includes computer executable instructions to review each of the number of counters to determine whether to discard the item based upon whether at least one of the counters indicates that a higher classification item is being held in the queue.
    Type: Application
    Filed: April 12, 2005
    Publication date: October 12, 2006
    Inventors: Lewis Kootstra, Jonathan Watts
  • Publication number: 20060215653
    Abstract: Systems, methods, and devices are provided for moving packets on a network device. One method includes receiving packets to a number of network chips, the number of network chips having a conduit port which can be selectively chosen to exchange packets with a processor responsible for processing packets. The method includes adding data for additional functionality to certain packets. Adding data includes encapsulating the certain packets to maintain an appearance of a certain packet format.
    Type: Application
    Filed: March 23, 2005
    Publication date: September 28, 2006
    Inventors: Bruce LaVigne, John Wickeraad, Lewis Kootstra, Jonathan Watts
  • Publication number: 20060187913
    Abstract: Network devices and methods are provided for device monitoring. One embodiment includes a network device having a processor, a high speed interconnect and a number of network chips. The number of network chips are coupled to one another through the high speed interconnect. The number of network chips have a conduit port which can be selectively chosen to exchange packets, received to any network chip, with the processor.
    Type: Application
    Filed: February 4, 2005
    Publication date: August 24, 2006
    Inventors: Bruce LaVigne, John Wickeraad, Lewis Kootstra, Jonathan Watts
  • Publication number: 20060176899
    Abstract: Network devices and methods are provided involving a support chip in association with network chips. One embodiment includes a network device having a processor, a high speed interconnect, and a number of network chips coupled to one another through the high speed interconnect. The number of network chips include a conduit port which can be selectively chosen to exchange packets, received to the number of network chips, with the processor. The support chip is coupled to the number of network chips in association with selecting a conduit port on one of the number of network chips to exchange packets with the processor.
    Type: Application
    Filed: February 8, 2005
    Publication date: August 10, 2006
    Inventors: Bruce Lavigne, John Wickeraad, Lewis Kootstra, Jonathan Watts
  • Publication number: 20050180249
    Abstract: A memory device includes a plurality of memory arrays, each memory array being coupled to an input data bus and an output data bus, a clock generator that generates an internal clock signal to form at least one transfer cycle to control timing of data transfer to and from the plurality of memory arrays, and a controller that controls read and write operations from and to the plurality of memory arrays. In one embodiment, the controller receives a command word containing at least a first command and a second command and executes the first and second command on the same transfer cycle.
    Type: Application
    Filed: April 11, 2005
    Publication date: August 18, 2005
    Inventor: Lewis Kootstra