Abstract: A sensing technique uses a variable precharge voltage sensing with a single bitline swing in a DRAM cell or array of DRAM cells so that the power dissipation is reduced. The bitline precharge voltage varies from one RAS cycle to the next RAS cycle depending upon the level of the data in the accessed cells. Such an arrangement eliminates the need for a reference voltage generator since the precharge voltage is not the same voltage for each RAS cycle.

Abstract: A folded bitline DRAM cell is described which includes a trench capacitor and a planar-configured access transistor. The access transistor is stacked over the capacitor and has a first terminal connected thereto. The access transistor includes a planar-oriented gate. A first wordline has a minor surface in contact with the gate and a major surface that is oriented orthogonally to the gate. An insulating pedestal is positioned adjacent the gate and a passing wordline is positioned on the pedestal, the passing wordline having a major surface parallel to the first wordline. In another embodiment, the folded bitline DRAM cell includes a vertically oriented access transistor having one terminal formed on the upper extent of a contact to the trench capacitor, to provide optimum electrical connection thereto.

Abstract: A sensing circuit for a dynamic random access memory structure is disclosed having first and second bit lines, one of the bit lines being a reference bit line which is held at a precharge voltage when a sense amplifier in the sensing circuit is latched, the sense amplifier includes first and second nodes and first, second, third and fourth transistor devices, the first and second transistor devices form an N-device cross-coupled pair and the third and fourth transistor devices form a P-device cross-coupled pair. The first node is connected to the first bit line and to the second and fourth transistor devices, and the second node is connected to the first and third transistor devices. A first isolation transistor device is connected to the first bit line and a second isolation transistor device is connected to the second bit line. A first clock signal line is connected to the first isolation transistor device and a second clock signal line is connected to the second isolation transistor device.

Abstract: A folded bitline DRAM cell is described which includes a trench capacitor and a planar-configured access transistor. The access transistor is stacked over the capacitor and has a first terminal connected thereto. The access transistor includes a planar-oriented gate. A first wordline has a minor surface in contact with the gate and a major surface that is oriented orthogonally to the gate. An insulating pedestal is positioned adjacent the gate and a passing wordline is positioned on the pedestal, the passing wordline having a major surface parallel to the first wordline. In another embodiment, the folded bitline DRAM cell includes a vertically oriented access transistor having one terminal formed on the upper extent of a contact to the trench capacitor, to provide optimum electrical connection thereto.

Abstract: An ECL circuit (12) for directly coupling to and from a CMOS circuit (10). The ECL circuit has an input node for receiving an input signal generated by a CMOS circuit. The input signal swings, or transitions, between a first potential (V.sub.0) and a second potential (V.sub.1). The ECL circuit further includes ECL core circuitry (Q.sub.3, Q.sub.4, R.sub.L), coupled to the input node and responsive the received signal, for generating an intermediate electrical signal that swings between a third potential (V.sub.2) and a fourth potential (V.sub.3) that is approximately two times (V.sub.1 -V.sub.0). The ECL circuit further includes an output driver circuit for coupling to an input of a CMOS circuit or to another ECL circuit. The output driver circuit has an input node coupled to an output of the ECL core circuitry and includes emitter followers (EF.sub.1, EF.sub.2) for generating, in response to the intermediate electrical signal swinging between V.sub.2 and V.sub.

Abstract: A vertical DRAM cell using VMOS transistors and trench capacitors and the fabrication process therefor. A vertical DRAM structure comprising a VMOS transistor and trench capacitor in combination is provided wherein the access transistors are in a V-groove and the capacitors are in two vertical layers. The structure has only a single level of polysilicon and has no contacts. The memory cell circuit is a one-device memory cell, having a single access transistor with its gate connected to a word line, its drain connected to a bit line, and its source connected to a storage capacitor. More particularly, the storage capacitance node is connected to the source of the V-groove access device through a conducting bridge. The gate of the V-groove access device is connected to the polysilicon word line and the drain is a diffused region which also serves as the bit line of the cell. An epitaxial layer is grown over a combination of single crystalline material and oxide.

Abstract: This invention relates generally to Dynamic Random Access Memory (DRAM) cells and more particularly relates to a DRAM cell wherein the storage capacitor of the cell is disposed in a trench formed in a semiconductor substrate. Still more particularly, it relates to a DRAM cell wherein at least a portion of the substrate is heavily doped and forms the counterelectrode of the storage capacitor while a heavily doped polycrystalline plug disposed in the trench capacitor forms the other electrode of the storage capacitor. The DRAM cell includes a field effect access transistor disposed in a well which is opposite in conductivity type to that of the substrate. The well itself is formed in a lightly doped portion of the substrate and may be n or p-type conductivity with the other portions of the cell having conductivity types appropriate for devices fabricated in the CMOS environment.

Abstract: A self-timed precharge circuit for a memory array consisting of an X-line complement circuit connected to the outputs of a plurality of falling edge detectors, and a precharge generator circuit connected to the output of the X-line complement circuit. Each falling edge detector is connected to a separate wordline (WL, WL+1, . . . WL+N) of the system memory array. In operation, the precharge generator circuit is triggered with a signal on the output lead from a falling edge detector which is activated when the selected wordline (WL, WL+1, . . . WL+N) connected thereto resets.

Abstract: A decoder/driver circuit for a semiconductor momory having a A1 to AN (true) and A1 to AN (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A .PHI.PC line is included for receiving a .PHI.PC precharge clock signal thereon and a .PHI.R line is provided for receiving a .PHI.R reset clock signal thereon. The decoder/driver circuit includes a NOR decoder means having a plurality of transistor switching devices connected to A1 to AN-1 or A1 to AN-1 of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on a decoder output node depending on the address bits state. The decoder/driver circuit further includes a selection means having a plurality of transistor devices connected to the output node of the decoder to produce a first selection signal when the decoder output node and the AN line is high and a second selection signal when the decoder output node and the AN line is high.

Abstract: A pipelined analog-to-digital (A/D) conversion system enhances the effective data rate of the converter in direct proportion to the number of stages in the pipeline. The pipelined A/D converter operates in conjunction with a charge-coupled device (CCD) multilevel storage (MLS) in a three-bit (eight-level) implementation. Three comparators are used in the three-bit system arranged in a sequential successive approximation configuration with control circuits and a CCD shift register.

Abstract: A digital-to-analog conversion (DAC) circuit and trigger comparator combination is described for encoding and decoding charge packets in a common-well multi-level signal charge-coupled memory device (CCD). The DAC circuit, which may be of the weighted capacitor type, is used to generate a staircase waveform and to create the common-well under a first gate in the CCD. The trigger comparator adjacent to a second gate in the CCD is a detection circuit which stays in one binary state until an input charge signal is received, whereupon it switches state. In particular, the weighted capacitor DAC contains an extra offset bit which is used in the analog-to-digital or regeneration operation such that when the trigger comparator switches state, the digital input to the DAC at that time correctly represents the signal charge being converted. In one embodiment a circular serial-parallel-serial memory structure is employed as the multi-level CCD memory system.

Abstract: A bucket brigade circuit is described for generating a sequence of packets of charge carriers of the form Q.sub.R /2, Q.sub.R /4, Q.sub.R /8....Q.sub.R /2.sup.N where N is an integer. The charge packets thus generated can be employed in combinations in either digital-to-analog or analog-to-digital converters. The charge generation circuit requires two equal capacitors which are used for charge redistribution. To obtain accurate quantities of charge in the generated charge packets the capacitors employed should be large, however the use of large capacitors results in low operating speed because of the large charge transfer time constants involved. The described circuit provides a scheme to reduce charge transfer time constants and therefore obtain greater speed while still permitting the use of large capacitors for high accuracy.

Abstract: Analog-to-digital (A/D) and digital-to-analog (D/A) converter circuits are provided using charge redistribution. The analog-to-digital converter circuit also employs successive approximation binary search techniques wherein the number of search voltages generated is a minimum. The analog-to-digital circuit includes a digital-to-analog converter circuit, a comparator circuit and a logic control means. The digital-to-analog circuit, under control of the logic means, accepts a reference voltage input and produces a sequence of search voltages which are compared with an unknown analog input voltage at the comparator. The resultant outputs from the comparator are applied to the control logic to determine the search voltage sequence. The digital-to-analog converter for the aforesaid circuit is provided in one embodiment employing charge-coupled-device technology.