Abstract: A frequency divider state machine synchronously divides an input clock's frequency by 1.5. The clock divider circuit includes two storage elements which are clocked on different edges of the input clock signal. The outputs of the two storage elements are combined together using combinatorial logic, the results of which are provided back to the inputs of the two storage elements. Further, the two outputs of the memory storage elements are combined together to provide the desired output frequency. Preferably, the circuit is designed such that if either of the two memory storage elements powers up in an undesired state, the divide by 1.5 circuit will automatically transition to one of the desired states and continue to provide the output frequency at the desired divide by 1.5 clock frequency after the initial transition. The circuit can be implemented as a digital circuit in an ASIC, an LSI, or the like.