Abstract: In order to alleviate lifting problems and to reduce the height of the stack, a tungsten layer is formed on a interpoly dielectric layer, such as an ONO layer, which separates the conductive control gate from a polysilicon floating gate that is in turn formed on a tunnel oxide layer. The tungsten layer is protected by the provision of a tungsten silicide cap which is formed over the tungsten layer and which therefore prevents oxidation of the metal. The two tungsten based layers are such as to replace the second polysilicon layer which is normally used to form the floating gate.

Abstract: A memory gate stack in a high density memory core has spaces on the order of less than 0.25 microns using conventional deep ultraviolet (DUV) lithography techniques by depositing a layer of silicon oxynitride over a plurality of layers, and a thin resist layer overlying on the silicon oxynitride layer. The resist layer has a thickness sufficient to withstand removal during etching of the silicon oxynitride layer, for example about 3,000 Angstroms to about 4,000 Angstroms. The silicon oxynitride layer has a sacrificial portion having a thickness at least about 500 Angstroms, and a stop-layer thickness, used for spacer formation following etching of the memory gate, of at least 1,000 Angstroms. The use of silicon oxynitride as an antireflective coating layer in combination with the thin resist optimizes the resolution of DUV lithography, enabling formation of spacers having widths less than about 0.24 microns.

Abstract: Methods and arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The methods and arrangements effectively reduce the severity of the topology attributable to the space between adjacent floating gates by advantageously tapering the sidewalls of the floating gates. The altered topology allows a subsequently formed control gate to be formed without significant surface depressions. Significant surface depressions in the control gate can lead to cracks in the suicide layer that is formed on the control gate. The cracking usually occurs during subsequent thermal processing of the semiconductor device. Thus the disclosed methods and arrangements prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.

Abstract: A soft-landing etch process is provided to form an oxide layer with uniform thickness on an open area between flash memory transistors on a substrate. A dielectric oxide layer, such as silicon dioxide, is formed on a semiconductor substrate. A polysilicon layer used to form gates of flash memory transistors is then formed on the oxide layer. The polysilicon layer is covered with a layer of conductive material, such as tungsten silicide (WSi). A cap polysilicon layer is deposited on the conductive layer. An anti-reflecting coating, such as SiON, is formed on the cap polysilicon layer. A photo-resist mask comprising a pattern defining a gate is formed on the surface of the anti-reflecting coating. The softlanding etch process performed to expose oxide layer on the substrate area between flash memory transistors includes three etch steps. The first etch step is carried out to remove materials covering the gate polysilicon layer on the area between flash memory transistors.

Abstract: The high density plasma metal etch rate of a conductive material within a dense array of conductive lines is increased to no less than the etch rate of the conductive material in a bordering open field by injecting a sufficient amount of nitrogen into the total gas flow of the plasma. The injection of nitrogen in amounts of about 15% and 50% by volume of the total gas flow effectively reduces the etch rate differential between the dense array and open field, thereby reducing overetching, resist loss, and oxide loss in the open field, and facilitating planarization.

Abstract: Undercutting of conductive lines in a dense array on a dielectric layer containing an open field is prevented by providing one or more non-functional components, such as one or more non-functional conductive lines, in the dielectric layer under the dense array of conductive lines.

Abstract: Undercutting of conductive lines in a dense array bordered by an open field is avoided by reducing the severity of etching when the conductive material in the open field is substantially removed. In a preferred embodiment, the flow rate of chlorine gas is reduced during high density chlorine plasma etching of a conductive pattern when the conductive material is substantially removed from the open field.

Abstract: A Ti.sub.x N.sub.y layer, not necessarily stoichiometric, is interposed between a titanium or aluminum interconnect layer to improve adhesion and prevent re-entrant undercutting and lifting of the interconnect layer during the process of patterning and plasma etching to form interconnect lines on a substrate, such as an oxide.

Abstract: A Ti.sub.x N.sub.y layer, not necessarily stoichiometric, is interposed between a titanium or aluminum interconnect layer to improve adhesion and prevent re-entrant undercutting and lifting of the interconnect layer during the process of patterning and plasma etching to form interconnect lines on a substrate, such as an oxide.

Abstract: A process is provided for forming a hard mask over an aluminum-containing layer for patterning and etching the aluminum-containing layer to define interconnects. The process comprises depositing the material comprising the hard mask at a temperature that is within the range of about 100.degree. C. below the sputtering temperature of the aluminum-containing metal and the sputtering temperature of the aluminum-containing metal.

Abstract: Undercutting of conductive lines in a dense array on a dielectric layer containing an open field is prevented by providing one or more non-functional components, such as one or more non-functional conductive lines, in the dielectric layer under the dense array of conductive lines.

Abstract: A method of forming and removing spacers used to mask lightly doped drain (LDD) regions in the formation of a field effect transistor (FET) involves depositing a thin oxide layer over the active region of a substrate and a gate structure formed on the active region. A polysilicon film is provided over the oxide and then doped using a POCl.sub.3 dopant. The polysilicon layer is then etched to form spacers at the ends of the gate and the spacers are used to mask lightly doped drain regions in the substrate during the implantation of source and drain regions. After the implant to form the source and drain regions, the device is subjected to a rapid thermal annealing for approximately 20-60 seconds at approximately 900.degree. C. in an inert atmosphere to cure any damage to the oxide layer which occurs during the source/drain implant. Curing the oxide layer reduces the etch rate of the oxide layer for an etchant which is designed to selectively etch the polysilicon spacers faster than it etches the oxide layer.