Abstract: A memory device includes a plurality of memory arrays, each memory array being coupled to an input data bus and an output data bus, a clock generator that generates an internal clock signal to form at least one transfer cycle to control timing of data transfer to and from the plurality of memory arrays, and a controller that controls read and write operations from and to the plurality of memory arrays. In one embodiment, the controller receives a command word containing at least a first command and a second command and executes the first and second command on the same transfer cycle.

Abstract: A system for performing an input processing function on a data packet. The system has an input port to which a first processor is coupled, which determines an attribute of the data packet, and a memory coupled to the first processor having a number of queues. The data packet is assigned to one of the queues based upon the attribute determined, which may be an indicator of a priority characterizing said data packet. Input processing is thus performed in a fixed amount of time, deferring variable latency operations until after the input memory.

Abstract: A device testing method and interface includes receiving a first command and a second command, selectively combining at least a portion of the second command with at least a portion of the first command to generate a test command, and transmitting the test command to the device. In one embodiment, combining the first and second commands reduces the number of test cycles required to test the device.

Abstract: A memory device includes a plurality of memory arrays, each memory array being coupled to an input data bus and an output data bus, a clock generator that generates an internal clock signal to form at least one transfer cycle to control timing of data transfer to and from the plurality of memory arrays, and a controller that controls read and write operations from and to the plurality of memory arrays. In one embodiment, the controller receives a command word containing at least a first command and a second command and executes the first and second command on the same transfer cycle.

Abstract: A device testing method and interface includes receiving a first command and a second command, selectively combining at least a portion of the second command with at least a portion of the first command to generate a test command, and transmitting the test command to the device. In one embodiment, combining the first and second commands reduces the number of test cycles required to test the device.

Abstract: A memory device includes a plurality of memory arrays, each memory array being coupled to an input data bus and an output data bus, a clock generator that generates an internal clock signal to form at least one transfer cycle to control timing of data transfer to and from the plurality of memory arrays, and a controller that controls read and write operations from and to the plurality of memory arrays. In one embodiment, the controller receives a command word containing at least a first command and a second command and executes the first and second command on the same transfer cycle.

Abstract: A system for performing an input processing function on a data packet. The system has an input port to which a first processor is coupled, which determines an attribute of the data packet, and a memory coupled to the first processor having a number of queues. The data packet is assigned to one of the queues based upon the attribute determined, which may be an indicator of a priority characterizing said data packet. Input processing is thus performed in a fixed amount of time, deferring variable latency operations until after the input memory.