Patents by Inventor Li A Wang

Li A Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230077887
    Abstract: The present disclosure discloses a detection kit and a preparation method thereof and a detection method for novel coronavirus, and relates to the technical field of biomedicine, including an antigen test strip. The antigen test strip includes a substrate, bibulous paper, immune nitrocellulose membrane, and immune microsphere pad. The immune microsphere pad, the immune nitrocellulose membrane and the bibulous paper are pasted on the substrate. The The immune microsphere pad is coated with latex microsphere-labeled novel coronavirus SARS-CoV-2 monoclonal antibody 1. The immune nitrocellulose membrane is provided with a test line coated with novel coronavirus SARS-CoV-2 monoclonal antibody 2 and a quality control line coated with goat anti-mouse IgG polyclonal antibody. The present disclosure uses latex particles as labeled tracer, and uses antigen-antibody reaction and lateral chromatography to detect and analyze targets, having advantages of convenience and swift.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 16, 2023
    Inventors: Li WANG, Lang CHEN
  • Publication number: 20230084277
    Abstract: A process for producing a barrier composition includes subjecting a siloxane compound having 1 to 3 amino groups and an aqueous solution including water and an alcohol to hydrolysis and first-stage condensation under required conditions, subjecting a first colloidal mixture obtained and an additional alcohol to second-stage condensation, subjecting a second colloidal mixture obtained, which has a particular solid content, to heating under required conditions, and subjecting a cured product obtained to aging under required conditions. A barrier composition produced by the process is also disclosed.
    Type: Application
    Filed: October 26, 2021
    Publication date: March 16, 2023
    Inventors: Chung-Kuang YANG, Yi-Hsuan LAI, Sheng-Tung HUANG, Kun-Li WANG
  • Publication number: 20230083518
    Abstract: Disclosed is an image segmentation method, including: obtaining an original image set; performing feature extraction on the original image set by using a backbone network to obtain a feature map set; performing channel extraction fusion processing on the feature map set by using a channel extraction fusion model to obtain an enhanced feature map set; and segmenting the enhanced feature map set by using a preset convolutional neural network to obtain an image segmentation result. In addition, the present application also provides an image segmentation system and device, and a readable storage medium, which have the beneficial effects above.
    Type: Application
    Filed: October 27, 2020
    Publication date: March 16, 2023
    Inventors: Li WANG, Zhenhua GUO, Nan WU, Yaqian ZHAO
  • Publication number: 20230082878
    Abstract: A semiconductor structure includes a semiconductor on insulator (SOI) substrate, a first electrically conductive structure, and a second electrically conductive structure. The SOI substrate includes a base substrate, a buried insulation layer disposed on the base substrate, a semiconductor layer disposed on the buried insulation layer, and a trap rich layer disposed between the buried insulation layer and the base substrate. At least a part of the first electrically conductive structure and at least a part of the second electrically conductive structure are disposed in the trap rich layer. A part of the trap rich layer is disposed between the first electrically conductive structure and the second electrically conductive structure. The first electrically conductive structure, the second electrically conductive structure, and the trap rich layer disposed between the first electrically conductive structure and the second electrically conductive structure are at least a portion of an anti-fuse structure.
    Type: Application
    Filed: October 14, 2021
    Publication date: March 16, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: BO TAO, Li Wang, Ching-Yang Wen, Purakh Raj Verma, ZHIBIAO ZHOU, DONG YIN, Gang Ren, Jian Xie
  • Patent number: 11602534
    Abstract: The present invention relates to a kinase inhibitor, comprising a compound of Formula I or a pharmaceutically acceptable salt, solvate, ester, acid, metabolite or prodrug thereof. The present invention also relates to a pharmaceutical composition comprising the kinase inhibitor, and to uses and methods for using these compounds and compositions to inhibit the activity of wild-type FLT3, mutant FLT3-ITD, PDGFR? and/or PDGFR? kinase in a cell or a subject, as well as uses and methods of these compounds and compositions to preventing or treating kinase-associated conditions in a subject.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: March 14, 2023
    Assignee: Hefei Institutes of Physical Science, Chinese Academy of Sciences
    Inventors: Qingsong Liu, Jing Liu, Xiaofei Liang, Beilei Wang, Kailin Yu, Zongru Jiang, Cheng Chen, Chen Hu, Wenchao Wang, Fengming Zou, Qingwang Liu, Feng Li, Wenliang Wang, Li Wang
  • Patent number: 11605684
    Abstract: An array substrate, including: a base substrate including a display area and a non-display area; a first transistor in the display area; a second transistor in the non-display area; and a substrate electrode, the substrate electrode including: a first substrate electrode between the first transistor and the base substrate; and a second substrate electrode between the second transistor and the base substrate, wherein the first substrate electrode and the second substrate electrode are configured to adjust threshold voltages of the first transistor and the second transistor, respectively, there is an open circuit between the first substrate electrode and the second substrate electrode, the first substrate electrode is supplied with a first adjustment voltage, the second substrate electrode is supplied with a second adjustment voltage, and an absolute value of the first adjustment voltage is different from an absolute value of the second adjustment voltage.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: March 14, 2023
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Li Wang
  • Patent number: 11600969
    Abstract: In order to provide a QCL element operating in the near-infrared wavelength range, the present disclosure provides a quantum cascade laser element 1000 having a semiconductor superlattice structure (QCL structure 100) sandwiched between a pair of conductive sections 20 and 30. The semiconductor superlattice structure serves as an active region that emits electromagnetic waves. The active region has a plurality of unit structures 10U that are stacked on top of each other. Each unit structure includes four well layers 10W1-10W4 of a composition of AlxGa1?xN, separated from each other by barrier layers 10B1-10B5 of a composition of AlyGa1?yN with 0?x<y?1. Both of the conductive sections in the pair of conductive sections have a refractive index lower than that of the active region in which doped TCO inserted as a key role.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: March 7, 2023
    Assignee: RIKEN
    Inventors: Li Wang, Hideki Hirayama
  • Publication number: 20230061022
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure and over the gate structure, a layer of organometallic material formed through the layer of dielectric material, and a trench conductor layer formed through the layer of dielectric material and in contact with the S/D contact structure and the gate structure. The layer of organometallic material can be between the layer of dielectric material and the trench conductor layer.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsu-Kai CHANG, Chia-Hung CHU, Shuen-Shin LIANG, Keng-Chu LIN, Pinyen LIN, Sung-Li WANG
  • Publication number: 20230068965
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a layer of dielectric material over the gate structure, a source/drain (S/D) contact layer formed through and adjacent to the gate structure, and a trench conductor layer over and in contact with the S/D contact layer. The S/D contact layer can include a layer of platinum-group metallic material and a silicide layer formed between the substrate and the layer of platinum-group metallic material. A top width of a top portion of the layer of platinum-group metallic material can be greater than or substantially equal to a bottom width of a bottom portion of the layer of platinum-group metallic material.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hung CHU, Shuen-Shin LIANG, Hsu-Kai CHANG, Tzu Pei CHEN, Kan-Ju LIN, Chien CHANG, Hung-Yi HUANG, Sung-Li WANG
  • Patent number: 11592029
    Abstract: The present application discloses an impeller for a centrifugal fan and a centrifugal fan. The impeller comprises a support member and several vanes. The support member has an inner wall that defines a hollow portion. The several vanes are arranged inside the hollow portion, each of the several vanes is connected with the inner wall and extends along the axial direction of the support member, and the several vanes are arranged along the circumferential direction of the support member. Each of the several vanes is bent and comprises a front edge, a tail edge, a convex suction surface, and a concave pressure surface, the suction surface and the pressure surface are arranged to oppose each other, and the front edge and the tail edge are arranged to oppose each other, wherein the tail edge is connected with the inner wall of the support member, and wherein several protrusions are provided on the suction surface, and the several protrusions are arranged to be close to the front edge.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: February 28, 2023
    Assignee: Air Distribution Technologies IP, LLC
    Inventors: Shifeng Feng, Xiaokui Ma, Li Wang
  • Patent number: 11594609
    Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: February 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin Liang, Chun-I Tsai, Chih-Wei Chang, Chun-Hsien Huang, Hung-Yi Huang, Keng-Chu Lin, Ken-Yu Chang, Sung-Li Wang, Chia-Hung Chu, Hsu-Kai Chang
  • Publication number: 20230058468
    Abstract: A method of fabricating an air gap includes receiving a first thickness information of an inter-metal dielectric layer formed on a substrate and receiving a second thickness information of an inter-layer dielectric layer formed on the substrate. Then, a first etching is performed, wherein the first etching includes etch the inter-metal dielectric layer based on a first etching control value corresponding to the first thickness information. After the first etching, a second etching is performed to etch the inter-layer dielectric layer based on a second etching control value corresponding to the second thickness information.
    Type: Application
    Filed: August 23, 2021
    Publication date: February 23, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: BO TAO, RUNSHUN WANG, Li Wang, Ching-Yang Wen, Purakh Raj Verma, DONG YIN, Jian Xie
  • Publication number: 20230053665
    Abstract: The invention relates to a sealing element with high sealing effect against air and moisture, which is easy to apply, and which moreover offers the possibility to reopen the sealed gap in an uncomplicated manner. Said solution is provided by an adhesive tape with differing adhesive power on the two main sides, which comprises a) a polymer foam layer and b) an outer adhesive compound layer and/or an outer thermoplastic film on one side of the polymer foam layer and is characterized in that, where the adhesive tape comprises an outer adhesive compound layer, the tape has a greater adhesive power on the side provided with the outer adhesive compound layer than on the opposing side and/or, where the adhesive tape comprises an outer thermoplastic film, the tape has a lower adhesive power on the side provided with the outer thermoplastic film than on the opposing side. The invention furthermore relates to the use of an adhesive tape according to the invention for sealing a joint between two components.
    Type: Application
    Filed: January 15, 2021
    Publication date: February 23, 2023
    Applicant: TESA SE
    Inventors: Li WANG, Deniz Nixk AKIN, Kim ELSENBACH, Hannes DAG
  • Publication number: 20230053595
    Abstract: A device includes a substrate, a gate structure wrapping around a vertical stack of nanostructure semiconductor channels, and a source/drain abutting the vertical stack and in contact with the nanostructure semiconductor channels. The device includes a gate via in contact with the first gate structure. The gate via includes a metal liner layer having a first flowability, and a metal fill layer having a second flowability higher than the first flowability.
    Type: Application
    Filed: August 19, 2021
    Publication date: February 23, 2023
    Inventors: Sheng-Tsung WANG, Lin-Yu HUANG, Cheng-Chi CHUANG, Sung-Li WANG, Chih-Hao WANG
  • Publication number: 20230048014
    Abstract: A pixel circuit includes a data writing sub-circuit and a leakage prevention sub-circuit. The data writing sub-circuit is coupled to a first scan signal terminal, a data signal terminal and a light-emitting control sub-circuit, and is configured to: in a data writing period, store a light-emitting compensation signal in response to a gate scan signal from the first scan signal terminal and a data signal from the data signal terminal; and in a light-emitting period, assist in controlling the light-emitting control sub-circuit to be turned on according to the light-emitting compensation signal. The leakage prevention sub-circuit is coupled to the data writing sub-circuit and an auxiliary voltage terminal that is configured to provide to a constant voltage, and is configured to: in the data writing period, store another light-emitting compensation signal; and in the light-emitting period, inhibit leakage of the data writing sub-circuit according to the another light-emitting compensation signal.
    Type: Application
    Filed: April 26, 2021
    Publication date: February 16, 2023
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Li WANG, Lujiang HUANGFU
  • Publication number: 20230049380
    Abstract: Disclosed are a low-silicon and low-carbon equivalent GPa grade multi-phase steel plate/steel strip and a manufacturing method therefor. The steel plate/steel strip comprises the following components in percentages by weight: 0.03-0.07% of C, 0.1-0.5% of Si, 1.7-2.0% of Mn, P<0.02%, S<0.01%, N<0.01%, 0.01-0.05% of Al, 0.4-0.7% of Cr, 0.001-0.005% of B, and 0.07-0.15% of Ti, and also comprises one or both of 0.15-0.4% of Mo or 0.02-0.08% of Nb, with the balance being Fe and other inevitable impurities; and at the same time, the steel plate/steel strip satisfies: the content of available B*>0.001, the content of available B*=B-[Ti-3.4N-1.2(C—Nb/7.8)]/22, CE<0.58, and CE=C+Mn/6+(Cr+Mo+V)/5+(Si+Ni+Cu)/15. The steel plate has a tensile strength of >980 MPa and a yield strength of >780 MPa, and the hole expansion rate satisfies: if an original hole is a punched hole, the hole expansion rate is >50%; and if the original hole is a reamed hole, the hole expansion rate is >60%.
    Type: Application
    Filed: December 30, 2020
    Publication date: February 16, 2023
    Applicant: BAOSHAN IRON & STEEL CO., LTD.
    Inventors: Hanlong ZHANG, Yiqiang SUN, Xinping MAO, Cheng WANG, Yulong ZHANG, Xinyan JIN, Shuize WANG, Li WANG
  • Publication number: 20230052592
    Abstract: Disclosed are a low-cost ultra-high-strength multiphase steel plate/steel strip and its manufacturing method. Said steel plate/steel strip comprises the following components in percentage by weight: 0.03 to 0.07% of C, 0.1 to 0.5% of Si, 1.3 to 1.9% of Mn, less than or equal to 0.02% of P, less than or equal to 0.01% of S, 0.01 to 0.05% of Al, 0.2 to 0.5% of Cr, 0.07 to 0.14% of Ti, less than 0.03% of (Ni+Nb+Mo+V), and the balance being Fe and other inevitable impurities; and Mn+1.5Cr+5(Ti+Al+Cu)+10(Mo+Ni)+20(Nb+V)<3.0; Mn+2Cr+4Ti+4Nb+4V+4Mo—Si/3+2C?3.0. The steel plate is mainly used for the manufacturing of automotive chassis and suspension system parts.
    Type: Application
    Filed: December 30, 2020
    Publication date: February 16, 2023
    Applicant: BAOSHAN IRON & STEEL CO., LTD.
    Inventors: Hanlong ZHANG, Yiqiang SUN, Xinping MAO, Yulong ZHANG, Cheng WANG, Xinyan JIN, Li WANG, Shuize WANG
  • Patent number: 11581259
    Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: February 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei Chang, Chien-Shun Liao, Sung-Li Wang, Shuen-Shin Liang, Shu-Lan Chang, Yi-Ying Liu, Chia-Hung Chu, Hsu-Kai Chang
  • Patent number: 11576387
    Abstract: The present invention discloses a method for preparing bread by fermentation with compounded sourdough, and belongs to the technical field of food. The method compounds saccharomycetes and lactic acid bacteria to prepare the compounded sourdough. Compared with spontaneous sourdough, the fermentation performance is similar, the quality is stable, the culture period is shortened, and the compounded sourdough can be used to replace the spontaneous sourdough to prepare bread by fermentation. Moreover, the nutritional value of the compounded sourdough bread is much higher than that of the commercial yeast bread using only a single type of yeast, both in terms of the total content of free amino acids and the content of essential amino acids. The compounded sourdough provided by the present invention has extremely high industrial application value.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: February 14, 2023
    Assignee: JIANGNAN UNIVERSITY
    Inventors: Li Wang, Yafang Yu, Juan Sun, Haifeng Qian, Yan Li
  • Patent number: D979657
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: February 28, 2023
    Inventor: Li Wang