Abstract: A high speed incrementer/decrementer design is presented that computes the propagate, generate, and kill signals which are used to compute carries and sums from the incrementer inputs. By setting one input to “0” and the carry-in to “1”, the adder is used as an incrementer. In the design of the invention, a bit-wise decision is made whether to complement the input bit or not. The design also allows decrementing and supports both unsigned and 2's complement number representations.

Abstract: Integrated circuit clock circuitry includes several clock nodes at different locations on a chip. Each node includes a clock wave input, a clock wave output and feedback circuitry for maintaining a predetermined phase relation between clock waves at the clock wave inputs and outputs. The clock wave input of one of the nodes is directly responsive to a clock wave of a clock wave source. A clock coupling circuit connected between each of the clock wave inputs (except the clock wave input of the node directly responsive to the clock wave source) and each of the clock wave outputs couples clock waves from the clock wave output of a first node to a clock wave input of a second node. Each of the coupling circuits includes feedback circuitry for maintaining a predetermined phase relation between clock waves the first node supplies to the coupling circuit and derived by the coupling circuit.

Abstract: A digital circuit for counting the number of zeroes or ones in a data word comprising a plurality of series paths leading to one-hot encoded outputs. Each one-hot encoded output indicates a different number of like signals in the input data word. One of the plurality of series paths is activated by connecting the series path from an input power rail to the one-hot output. A series path is connected through a plurality of transfer gates, each controlled by either a single bit of the input data word or its complement. The series paths may be optimized to share transfer gates by interconnecting them in a tree or lattice structure. Subsections of the input data word may be counted separately in independent tree or lattice structures, then combined in subsequent combinational stages of the circuit. The resulting one-hot encoded count of like signals may then be binary encoded by a final stage of the counting circuit.