Abstract: The present disclosure relates to a power factor correction circuit, a control method, and an electrical appliance. The power factor correction circuit may include: a power regulation branch, including a first switching unit, a second switching unit and a branch sampling resistor connected in series sequentially; an inductive branch, connected between an AC power source and a power regulation branch; a rectifier branch, including a first rectifier unit and a second rectifier unit, the rectifier branch may include a main line sampling resistor; a capacitance branch; a control circuit sampling a branch current flowing through each of the branch sampling resistors and a main line current flowing through the main line sampling resistor respectively, and controlling the switching of each power regulation branch sequentially. With the branch sampling resistor and the main line sampling resistor, the overall cost of the power factor correction circuit may be reduced.

Abstract: Disclosed are a method and control device for adjusting an opening size of a sampling window of a biopsy surgical device. The biopsy surgical device includes a motor, an outer cutter tube and an inner cutter tube. The outer cutter tube includes a sampling window on a side of the front end. The motor drives the inner cutter tube to move axially through a transmission mechanism, changing the axial relative position of the inner cutter tube and the sampling window. The method includes: obtaining an input instruction that includes a set value of an sampling window opening length; determining an axial movement distance of the inner cutter tube according to the current position of the inner cutter tube and the set value; calculating the number of rotations of the motor corresponding to the axial movement distance; and controlling the motor to rotate until the sampling window reaches the opening length.

Abstract: An integrated circuit device having functional circuitry driven by a clock signal includes onboard clock generation circuitry. The clock generation circuitry includes an input configured to accept a frequency reference signal, at least one variable loading capacitor coupled to the input for converting the crystal resonator signal into a calibrated clock signal, and calibration circuitry configured to calibrate the at least one variable loading capacitor based on a reference voltage. The input configured to accept a frequency reference signal may be configured to accept a crystal resonator signal.

Abstract: An integrated circuit device having functional circuitry driven by a clock signal includes onboard clock generation circuitry. The clock generation circuitry includes an input configured to accept a frequency reference signal, at least one variable loading capacitor coupled to the input for converting the crystal resonator signal into a calibrated clock signal, and calibration circuitry configured to calibrate the at least one variable loading capacitor based on a reference voltage. The input configured to accept a frequency reference signal may be configured to accept a crystal resonator signal.

Abstract: An integrated circuit device, having functional circuitry driven by a clock signal, includes a first clock path for accepting an external clock signal where the first clock path includes first biasing circuitry configured to controllably pass the external clock signal, a second clock path for accepting an external frequency reference signal where the second clock path includes internal clock generation circuitry configured to generate an internal clock signal from the external frequency reference signal and second biasing circuitry configured to controllably pass the external frequency reference signal to the internal clock generation circuitry, and selector circuitry configured to select, based on user input, a clock output to drive the functional circuitry of the integrated circuit device. The clock output is selected from between (i) an output of the first clock path, and (ii) an output of the second clock path.

Abstract: An integrated circuit device, having functional circuitry driven by a clock signal, includes a first clock path for accepting an external clock signal where the first clock path includes first biasing circuitry configured to controllably pass the external clock signal, a second clock path for accepting an external frequency reference signal where the second clock path includes internal clock generation circuitry configured to generate an internal clock signal from the external frequency reference signal and second biasing circuitry configured to controllably pass the external frequency reference signal to the internal clock generation circuitry, and selector circuitry configured to select, based on user input, a clock output to drive the functional circuitry of the integrated circuit device. The clock output is selected from between (i) an output of the first clock path, and (ii) an output of the second clock path.

Abstract: An integrated circuit device having functional circuitry driven by a clock signal includes onboard clock generation circuitry. The clock generation circuitry includes an input configured to accept a frequency reference signal, at least one variable loading capacitor coupled to the input for converting the crystal resonator signal into a calibrated clock signal, and calibration circuitry configured to calibrate the at least one variable loading capacitor based on a reference voltage. The input configured to accept a frequency reference signal may be configured to accept a crystal resonator signal.

Abstract: The present disclosure relates to a power factor correction circuit, a control method, and an electrical appliance. The power factor correction circuit may include: a power regulation branch, including a first switching unit, a second switching unit and a branch sampling resistor connected in series sequentially; an inductive branch, connected between an AC power source and a power regulation branch; a rectifier branch, including a first rectifier unit and a second rectifier unit, the rectifier branch may include a main line sampling resistor; a capacitance branch; a control circuit sampling a branch current flowing through each of the branch sampling resistors and a main line current flowing through the main line sampling resistor respectively, and controlling the switching of each power regulation branch sequentially. With the branch sampling resistor and the main line sampling resistor, the overall cost of the power factor correction circuit may be reduced.

Abstract: The present invention relates to a compound having a benzo seven-membered ring structure, and a preparation method therefor, and use thereof. The compound has a structure as represented by formula (I). Provided is use of the compound having the structure and prepared with the preparation method of the present invention, enantiomers, diastereomers, racemates and mixtures thereof of the compound, as well as chemically acceptable salts, crystalline hydrates and solvent mixtures of the compound and the enantiomers, diastereomers, racemates and mixtures thereof of the compound in the preparation of drugs for treating BET Bromodomain BRD4 activity or expression level related diseases.

Abstract: Methods for treating a neurological disorder, such as a traumatic spinal cord injury or traumatic brain injury, or a disorder such as Parkinson's disease or multiple sclerosis are provided. Such methods include administering a therapeutically effective amount of Gsx1 protein (such as a Gsx1-cell penetrating peptide fusion protein), or a nucleic acid molecule encoding such a protein (for example as part of a viral vector), thereby treating the neurological disorder.

Abstract: An intra frame bit rate allocation method being performed by a computer device comprising at least one processor, includes when a current frame of picture is an intra frame in a specified frame sequence, pre-encoding the current frame of picture; calculating a corresponding intra frame encoding cost and an inter frame encoding cost of the pre-encoding; and allocating an intra frame bit rate according to the calculated intra frame encoding cost and the inter frame encoding cost.

Abstract: An oscillator circuit includes a first current generator circuit that generates a current complementary to absolute temperature and a second current generator that generates a current proportional to absolute temperature. A temperature slope control circuit adjusts slopes of the current complementary to absolute temperature and the current proportional to absolute temperature in a complementary fashion and adds the current complementary to absolute temperature to the current proportional to absolute temperature after slope control to produce a temperature independent current. A current control circuit adjusts magnitude of the temperature independent current to produce a magnitude adjusted temperature independent current. A current controlled oscillator generates an output signal as a function of the magnitude adjusted temperature independent current.

Abstract: A video encoding method is provided. The video encoding method includes: obtaining a to-be-coded video frame; determining a current encoding mode according to current coding information and/or image feature information of the to-be-coded video frame; processing the to-be-coded video frame according to the current encoding mode to generate a current coded video frame; obtaining a current reference frame corresponding to the current coded video frame based on the current coded video frame being an inter frame; obtaining a corresponding processing reference frame according to resolution values of the current reference frame and the current coded video frame; and encoding the current coded video frame according to the processing reference frame to generate first coded data.

Abstract: A method for debugging a program includes executing, by a computing platform, a given program with a plurality of loops. Each of the plurality of loops includes multiple candidate iterations, and each loop in the given program includes a set of executable statements. A particular loop of the plurality of loops can include at least a particular iteration and one or more other iterations. The method can also include executing at least the particular iteration and the one or more other iterations for the particular loop. During execution of at least the particular iteration and the one or more other iterations for the particular loop, information that indicates which iteration of the particular loop is being executed is stored. Further, the method includes discarding temporarily stored information about the one or more other iterations without storing the information in the log.

Abstract: A method for debugging a program includes executing, by a computing platform, a given program with a plurality of loops. Each of the plurality of loops includes multiple candidate iterations, and each loop in the given program includes a set of executable statements. A particular loop of the plurality of loops can include at least a particular iteration and one or more other iterations. The method can also include executing at least the particular iteration and the one or more other iterations for the particular loop. During execution of at least the particular iteration and the one or more other iterations for the particular loop, information that indicates which iteration of the particular loop is being executed is stored. Further, the method includes discarding temporarily stored information about the one or more other iterations without storing the information in the log.

Abstract: A wind power converter device is provided. The wind power converter device includes grid side converters, generator side converters and a DC bus module. Each of the grid side converters includes grid side outputs electrically coupled to a grid and a first and a second DC inputs. Each two of the neighboring grid side converters are connected in series at the second and the first DC inputs. Each of the generator side converters includes generator side inputs electrically coupled to a generator device and a first and a second DC outputs. Each two of the neighboring generator side converters are coupled in series at the second and the first DC outputs. The DC bus module is electrically coupled between the grid side converters and the generator side converters.