Abstract: A method performed by at least one processor includes the following steps: generating a layout of an integrated circuit (IC), the layout comprising a cell and a layout context in a vicinity of the cell; receiving from a library a set of context groups and a set of timing tables, wherein each of the context groups is associated with one of the set of timing tables; determining a representative context group for the cell through comparing the layout context of the cell with the set of context groups; and performing a timing analysis on the layout according to a representative timing table associated with the representative context group for the cell.

Abstract: A connector device comprising: a housing made of an insulating material, which has a groove including connection terminals for coming into electrical contact with a row array of connection terminals of a first circuit board inserted therein and with a second circuit board, the first circuit board being partially housed in the groove; latching means having a pair of metal strips mutually oppositely provided one at each end of the housing at an interval corresponding to a length of the first circuit board in a direction in which the connection terminals are arranged as the row array; the pair of metal strips elastically holding the partially inserted first circuit board therebetween under an elastic force acting in a direction perpendicular to that in which the connection terminals of the first circuit board are arranged as the row array; holding means for holding the latching means relative to the housing; and fixing means for positionally fixing the first circuit board, which is held by the latching means, re