Patents by Inventor LI-CHEN LEE

LI-CHEN LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240150699
    Abstract: An electroporation system including one or more of a pipette, a pipette tip, a pipette docking assembly, and a pulse generator. The pipette docking assembly includes a pipette station, a pipette station guard, and a reservoir (e.g., a buffer tube). A method for transfecting a cell with a payload including providing an electroporation system, providing the cell, providing the payload, introducing the cell and the payload into a pipette tip, and electroporating the cell within the pipette tip by operating the electroporation system.
    Type: Application
    Filed: September 15, 2023
    Publication date: May 9, 2024
    Inventors: Han WEI, Chee Wai CHAN, Wui Khen LIAW, Shan Hua DONG, See Chen GOH, Huei Steven YEO, Harmon Cosme SICAT, JR., Mio Xiu Lu LING, Josh M. MEAD, Mikko MAKINEN, Beng Heng LIM, Kuan Moon BOO, Justina Linkai BONG, Chye Sin NG, Wee Liam LIM, Li Yang LIM, Way Xuang LEE
  • Publication number: 20240136376
    Abstract: A chip package structure and a method for fabricating the same are provided. The chip package structure includes a conductive substrate, a chip, a molding layer and a package cover. The conductive substrate has first and second board surfaces opposite to each other, and a die-bonding region is defined on the first board surface. The chip is disposed on the first board and located in the die-bonding region, and is electrically connected to the conductive substrate. The molding layer is disposed on the first board surface and surrounds the die-bonding region and the chip. The package cover is disposed on the molding layer, and the package cover, the molding layer and the conductive substrate jointly define an enclosed space surrounding the chip. Two of the conductive substrate, the molding layer and the package cover are connected to each other through a mortise-tenon joint structure.
    Type: Application
    Filed: March 10, 2023
    Publication date: April 25, 2024
    Inventors: DONG-RU WU, CHIEN-CHEN LEE, LI-CHUN HUNG
  • Publication number: 20240136202
    Abstract: A chip package structure and a method for producing the same are provided. The method at least includes: providing a substrate; placing a chip upside-down on the substrate; forming bonding wires coupled with the chip and the substrate; forming a support body on the substrate; providing at least one reflecting member at a periphery of the support body; providing a package cover adhered to a top surface of the support body; performing a solidifying process in which a solidifying light beam is emitted to the reflecting member and the reflecting member reflects the solidifying light beam to the support body to solidify the support body; performing a packaging process in which a package layer is formed to cover the chip, an outer periphery of the support body, and the package cover; and performing a cutting process to form the chip package structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 25, 2024
    Inventors: LI-CHUN HUNG, JUI-HUNG HSU, CHIEN-CHEN LEE
  • Publication number: 20240136386
    Abstract: A chip package structure and a method for producing the same are provided. The method at least includes: providing a substrate; forming a mirror ink on the substrate; placing a chip upside-down on the substrate; forming soldering wires coupled with the chip and the substrate; forming a support body on the substrate; providing a package cover adhered to a top surface of the support body; performing a solidifying process in which a solidifying light beam is emitted to the mirror ink and the mirror ink reflects the solidifying light beam to the support body to solidify the support body; performing a packaging process in which a package layer is formed to cover the chip, an outer periphery of the support body, and the package cover; and performing a cutting process in which the package layer and the substrate are cut to form the chip package structure.
    Type: Application
    Filed: March 15, 2023
    Publication date: April 25, 2024
    Inventors: LI-CHUN HUNG, JUI-HUNG HSU, CHIEN-CHEN LEE
  • Patent number: 11967652
    Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: April 23, 2024
    Assignee: TONG HSING ELECTRONIC INDUSTRIES, LTD.
    Inventors: Fu-Chou Liu, Jui-Hung Hsu, Yu-Chiang Peng, Chien-Chen Lee, Ya-Han Chang, Li-Chun Hung
  • Publication number: 20240088179
    Abstract: A chip packaging structure and a chip packaging method are provided. The chip packaging structure includes a first substrate, an image sensing chip, a supporting member, a second substrate, and an encapsulant. The image sensing chip is disposed on an upper surface of the first substrate, and the image sensing chip has an image sensing region. The supporting member is disposed on an upper surface of the image sensing chip and surrounds the image sensing region. The supporting member is formed by stacking microstructures with each other, so that the supporting member has pores. The second substrate is disposed on an upper surface of the supporting member, and the second substrate, the supporting member, and the image sensing chip define an air cavity. The encapsulant is attached to the upper surface of the first substrate and a side surface of the second substrate and filled into the pores.
    Type: Application
    Filed: October 18, 2022
    Publication date: March 14, 2024
    Applicant: TONG HSING ELECTRONIC INDUSTRIES, LTD.
    Inventors: You-Wei Chang, Chien-Chen Lee, Li-Chun Hung
  • Publication number: 20230352346
    Abstract: A method for manufacturing a semiconductor device includes forming a metal-including layer over a semiconductor substrate; forming a hydrophobic polymer layer over the metal-including layer; and forming an amphiphilic polymer layer between the metal-including layer and the hydrophobic polymer layer so as to enhance a bonding force therebetween.
    Type: Application
    Filed: April 27, 2022
    Publication date: November 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Chen LEE, Ren-Kai CHEN, Ying-Liang CHUANG, Ming-Hsi YEH, Kuo-Bin HUANG
  • Publication number: 20230343820
    Abstract: A method of forming a semiconductor device includes forming an epitaxial source/drain (S/D) structure adjacent to a gate structure; forming a dielectric structure over the gate and epitaxial S/D structures; forming a trench in the dielectric structure to accessibly expose a portion of the epitaxial S/D structure; forming a contact feature from the portion of the epitaxial S/D structure within the trench; and forming a S/D contact in the trench to be in contact with the contact feature overlying the epitaxial S/D structure. Forming the contact feature includes forming a metallic layer in the trench; performing a thermal process on the metallic layer to form the contact feature, where after the thermal process, metallic residues remain on a sidewall of a spacer of the dielectric structure in the trench; and removing the metallic residues by using a wet etching process, wherein the spacer of the dielectric structure remains substantially intact.
    Type: Application
    Filed: April 21, 2022
    Publication date: October 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ren-Kai Chen, Li-Chen Lee, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 11794164
    Abstract: Methods of making a poly(propylenimine) (PPI) sorbent, a PPI sorbent, structures including the PPI sorbent, methods of separating CO2 using the PPI sorbent, and the like, are disclosed.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: October 24, 2023
    Assignees: Georgia Tech Research Corporation, Global Thermostat Operations, LLC
    Inventors: Simon Pang, Christopher W. Jones, Li-Chen Lee, Miles Sakwa-Novak, Michele Sarazen
  • Publication number: 20220367206
    Abstract: An etchant for etching a cobalt-containing member in a semiconductor structure includes a fluorine-free acid and an alkaline solution, a rate of etching a cobalt-containing member by the etchant is greater than a rate of etching a nitride-containing member by the etchant, and a level of dissolved oxygen of the etchant is less than or equal to 100 ppb. A semiconductor structure, includes a plurality of epitaxial structures over a substrate, a gate structure over the substrate and between two of the plurality of epitaxial structures; a cobalt-containing member over one of the epitaxial structures and adjacent to the gate structure; and a dielectric member over the cobalt-containing member, wherein a top surface of the cobalt-containing member is formed by etching a portion of the cobalt-containing member using an etchant including a fluorine-free acid and an alkaline solution.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Inventors: REN-KAI CHEN, LI-CHEN LEE, SHUN WU LIN, MING-HSI YEH, KUO-BIN HUANG
  • Publication number: 20220355271
    Abstract: Methods of making a poly(propylenimine) (PPI) sorbent, a PPI sorbent, structures including the PPI sorbent, methods of separating CO2 using the PPI sorbent, and the like, are disclosed.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 10, 2022
    Inventors: Simon PANG, Christopher W. JONES, Li-Chen LEE, Miles SAKWA-NOVAK, Michele SARAZEN
  • Patent number: 11476124
    Abstract: A method of etching a cobalt-containing member in a semiconductor structure includes providing an etchant including a fluorine-free acid and an alkaline solution having a pH value between 8.5 and 13, and etching the cobalt-containing member in the semiconductor structure using the etchant, wherein a rate of etching the cobalt-containing member by the etchant is substantially greater than a rate of etching a nitride-containing member by the etchant. An etchant for etching a cobalt-containing member in a semiconductor structure includes a fluorine-free acid, and an alkaline solution having a pH value between 8.5 and 13; wherein a rate of etching a cobalt-containing member by the etchant is substantially greater than a rate of etching a nitride-containing member by the etchant, and a level of dissolved oxygen of the etchant is substantially less than or equal to 100 ppb.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ren-Kai Chen, Li-Chen Lee, Shun Wu Lin, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 11446634
    Abstract: Methods of making a poly(propylenimine) (PPI) sorbent, a PPI sorbent, structures including the PPI sorbent, methods of separating CO2 using the PPI sorbent, and the like, are disclosed.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: September 20, 2022
    Assignees: Georgia Tech Research Corporation, Global Thermostat Operations, LLC
    Inventors: Simon H. Pang, Christopher W. Jones, Li-Chen Lee, Miles A. Sakwa-Novak, Michele Sarazen
  • Publication number: 20220216066
    Abstract: A method of etching a cobalt-containing member in a semiconductor structure includes providing an etchant including a fluorine-free acid and an alkaline solution having a pH value between 8.5 and 13, and etching the cobalt-containing member in the semiconductor structure using the etchant, wherein a rate of etching the cobalt-containing member by the etchant is substantially greater than a rate of etching a nitride-containing member by the etchant. An etchant for etching a cobalt-containing member in a semiconductor structure includes a fluorine-free acid, and an alkaline solution having a pH value between 8.5 and 13; wherein a rate of etching a cobalt-containing member by the etchant is substantially greater than a rate of etching a nitride-containing member by the etchant, and a level of dissolved oxygen of the etchant is substantially less than or equal to 100 ppb.
    Type: Application
    Filed: January 5, 2021
    Publication date: July 7, 2022
    Inventors: REN-KAI CHEN, LI-CHEN LEE, SHUN WU LIN, MING-HSI YEH, KUO-BIN HUANG
  • Publication number: 20190291077
    Abstract: Methods of making a poly(propylenimine) (PPI) sorbent, a PPI sorbent, structures including the PPI sorbent, methods of separating CO2 using the PPI sorbent, and the like, are disclosed.
    Type: Application
    Filed: November 14, 2017
    Publication date: September 26, 2019
    Inventors: SIMON H. PANG, CHRISTOPHER W. JONES, LI-CHEN LEE, MILES A. SAKWA-NOVAK, MICHELE SARAZEN