Patents by Inventor Li-Chieh Chen
Li-Chieh Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978773Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a base structure. The semiconductor device structure also includes a first epitaxial structure and a second epitaxial structure sandwiching the channel structures. The semiconductor device structure further includes a gate stack wrapped around each of the channel structures and a backside conductive contact connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the base structure, and a second portion of the backside conductive contact extends upwards to approach a bottom surface of the second epitaxial structure. In addition, the semiconductor device structure includes an insulating spacer between a sidewall of the base structure and the backside conductive contact.Type: GrantFiled: March 25, 2021Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Shih-Chuan Chiu, Cheng-Chi Chuang, Chih-Hao Wang
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Publication number: 20240142878Abstract: Example implementations described herein include a laser source and associated methods of operation that can balance or reduce uneven beam profile problem and even improve plasma heating efficiency to enhance conversion efficiency and intensity for extreme ultraviolet radiation generation. The laser source described herein generates an auxiliary laser beam to augment a pre-pulse laser beam and/or a main-pulse laser beam, such that uneven beam profiles may be corrected and/or compensated. This may improve an intensity of the laser source and also improve an energy distribution from the laser source to a droplet of a target material, effective to increase an overall operating efficiency of the laser source.Type: ApplicationFiled: January 10, 2024Publication date: May 2, 2024Inventors: Tai-Yu CHEN, Shang-Chieh CHIEN, Sheng-Kang YU, Li-Jui CHEN, Heng-Hsin LIU
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Patent number: 11955515Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.Type: GrantFiled: July 28, 2022Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Chuan Chiu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Yu-Ming Lin
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Patent number: 11948702Abstract: A radiation source apparatus includes a vessel, a laser source, a collector, a horizontal obscuration bar, and a reflective mirror. The vessel has an exit aperture. The laser source is configured to emit a laser beam to excite a target material to form a plasma. The collector is disposed in the vessel and configured to collect a radiation emitted by the plasma and to reflect the collected radiation to the exit aperture of the vessel. The horizontal obscuration bar extends from a sidewall of the vessel at least to a position between the laser source and the exit aperture of the vessel. The reflective mirror is in the vessel and connected to the horizontal obscuration bar.Type: GrantFiled: May 5, 2023Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Chung Tu, Sheng-Kang Yu, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
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Publication number: 20240103378Abstract: The present disclosure provides an extreme ultraviolet (EUV) lithography system including a radiation source and an EUV control system integrated with the radiation source. The EUV control system includes a 3-dimensional diagnostic module (3DDM) designed to collect a laser beam profile of a laser beam from the radiation source in a 3-dimensional (3D) mode, an analysis module designed to analyze the laser beam profile, a database designed to store the laser beam profile, and an EUV control module designed to adjust the radiation source. The analysis module is coupled with the database and the EUV control module. The database is coupled with the 3DDM and the analysis module. The EUV control module is coupled with the analysis module and the radiation source.Type: ApplicationFiled: November 30, 2023Publication date: March 28, 2024Inventors: Tai-Yu CHEN, Tzu-Jung PAN, Kuan-Hung CHEN, Sheng-Kang YU, Shang-Chieh CHIEN, Li-Jui CHEN, Heng-Hsin LIU
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Publication number: 20240096996Abstract: A semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. The dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. The isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Lo-Heng Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20230207524Abstract: A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first processing element, a first I/O element, a second processing element, and a second I/O element. The first processing element is on a substrate. The first I/O element is on the substrate and electrically connected to the first processing element. The second processing element is on the substrate. The second I/O element is on the substrate and electrically connected to the second processing element. The first I/O element is electrically connected to and physically separated from the second I/O element.Type: ApplicationFiled: February 28, 2023Publication date: June 29, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chang Chi LEE, Jung Jui KANG, Chiu-Wen LEE, Li Chieh CHEN
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Patent number: 11594518Abstract: A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first processing element, a first I/O element, a second processing element, and a second I/O element. The first processing element is on a substrate. The first I/O element is on the substrate and electrically connected to the first processing element. The second processing element is on the substrate. The second I/O element is on the substrate and electrically connected to the second processing element. The first I/O element is electrically connected to and physically separated from the second I/O element.Type: GrantFiled: June 3, 2021Date of Patent: February 28, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chang Chi Lee, Jung Jui Kang, Chiu-Wen Lee, Li Chieh Chen
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Publication number: 20220392871Abstract: A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first processing element, a first I/O element, a second processing element, and a second I/O element. The first processing element is on a substrate. The first I/O element is on the substrate and electrically connected to the first processing element. The second processing element is on the substrate. The second I/O element is on the substrate and electrically connected to the second processing element. The first I/O element is electrically connected to and physically separated from the second I/O element.Type: ApplicationFiled: June 3, 2021Publication date: December 8, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chang Chi LEE, Jung Jui KANG, Chiu-Wen LEE, Li Chieh CHEN
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Patent number: 11461888Abstract: The disclosure provides a method and an image processor for computing decay factors for display degradation compensation. The method includes the following steps. A sequence of frames including a current frame are received. Whether the current frame is a dynamic frame or a static frame is determined. When the current frame is the dynamic frame, accumulation on decay factors is performed. When the current frame is the static frame, accumulation on the decay factors is not performed.Type: GrantFiled: July 20, 2020Date of Patent: October 4, 2022Assignee: Novatek Microelectronics Corp.Inventors: Li-Chieh Chen, Yen-Tao Liao
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Publication number: 20220020133Abstract: The disclosure provides a method and an image processor for computing decay factors for display degradation compensation. The method includes the following steps. A sequence of frames including a current frame are received. Whether the current frame is a dynamic frame or a static frame is determined. When the current frame is the dynamic frame, accumulation on decay factors is performed. When the current frame is the static frame, accumulation on the decay factors is not performed.Type: ApplicationFiled: July 20, 2020Publication date: January 20, 2022Applicant: Novatek Microelectronics Corp.Inventors: Li-Chieh Chen, Yen-Tao Liao
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Patent number: 10943531Abstract: The present invention provides a decay factor accumulation method for an organic light-emitting diode (OLED) display panel with a variable refresh rate (VRR). The decay factor accumulation method includes detecting an operating frame rate of an input image; generating a decay factor compensation coefficient according to the operating frame rate and a measurement frame rate; and generating a plurality of accumulated decay factors of the input image according to a decay factor lookup table corresponding to the measurement frame rate and the decay factor compensation coefficient.Type: GrantFiled: June 3, 2020Date of Patent: March 9, 2021Assignee: NOVATEK Microelectronics Corp.Inventors: Li-Chieh Chen, Yen-Tao Liao
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Patent number: 10277121Abstract: A charge pump circuit includes a first switch˜a fourth switch, a capacitor, a current source, a first resistor, a second resistor, an amplifier, another current source, a current mirror, a skip detection circuit, a switch generation circuit and a control unit. A method includes: (a) starting the charge pump circuit; (b) operating the charge pump circuit in a first phase, wherein the first switch and second switch are conducted and the third switch and fourth switch are disconnected; (c) operating the charge pump circuit in a second phase, wherein the third switch and fourth switch are conducted and the first switch and second switch are disconnected; (d) determining whether a detected voltage in the skip detection circuit is higher than a threshold voltage; and (e) selectively performing step (b) or (c) again according to determination result of step (d).Type: GrantFiled: August 1, 2018Date of Patent: April 30, 2019Assignee: Raydium Semiconductor CorporationInventors: Pei-Kai Tseng, Li-Chieh Chen, Chih-Jen Hung
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Publication number: 20190044437Abstract: A charge pump circuit includes a first switch˜a fourth switch, a capacitor, a current source, a first resistor, a second resistor, an amplifier, another current source, a current mirror, a skip detection circuit, a switch generation circuit and a control unit. A method includes: (a) starting the charge pump circuit; (b) operating the charge pump circuit in a first phase, wherein the first switch and second switch are conducted and the third switch and fourth switch are disconnected; (c) operating the charge pump circuit in a second phase, wherein the third switch and fourth switch are conducted and the first switch and second switch are disconnected; (d) determining whether a detected voltage in the skip detection circuit is higher than a threshold voltage; and (e) selectively performing step (b) or (c) again according to determination result of step (d).Type: ApplicationFiled: August 1, 2018Publication date: February 7, 2019Inventors: Pei-Kai TSENG, Li-Chieh CHEN, Chih-Jen HUNG
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Patent number: 10140916Abstract: A charge pump and operating method thereof are disclosed. The charge pump includes a first capacitor to a third capacitor and a first switch to a tenth switch. The charge pump is used to receive an input voltage and provide an output voltage to a load capacitor. When the charge pump is operated in a first mode, the charge pump controls the second capacitor failure, the output voltage and the input voltage have opposite electricity and the output voltage is (?½) times the input voltage. When the charge pump is operated in a second mode, the charge pump controls the second capacitor failure, the output voltage and the input voltage have opposite electricity and the output voltage is (??) times the input voltage.Type: GrantFiled: February 1, 2018Date of Patent: November 27, 2018Assignee: DAZZO TECHNOLOGY CORPORATIONInventors: Li-Chieh Chen, Hsuan-Hao Chien, Chih-Jen Hung
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Publication number: 20180226017Abstract: A charge pump and operating method thereof are disclosed. The charge pump includes a first capacitor to a third capacitor and a first switch to a tenth switch. The charge pump is used to receive an input voltage and provide an output voltage to a load capacitor. When the charge pump is operated in a first mode, the charge pump controls the second capacitor failure, the output voltage and the input voltage have opposite electricity and the output voltage is (?½) times the input voltage. When the charge pump is operated in a second mode, the charge pump controls the second capacitor failure, the output voltage and the input voltage have opposite electricity and the output voltage is (??) times the input voltage.Type: ApplicationFiled: February 1, 2018Publication date: August 9, 2018Inventors: Li-Chieh Chen, Hsuan-Hao Chien, Chih-Jen Hung
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Patent number: 9134738Abstract: A voltage converter is disclosed. The voltage converter includes a constant on time signal generator, a first and second transistors, an inductor, a feedback circuit and a ripple injection circuit. The constant on time signal generator generates a first and second driving signals for driving the first and second transistors. The voltage converter generates an output signal at an output end thereof. The feedback circuit divides the output signal to generate a feedback signal at a feedback end of the voltage converter. The ripple injection circuit gets the voltage of the feedback end and the voltage of the phase end to generate a injection signal. The constant on time signal generator generates the first and second driving signals according to the injection signal, the output signal and a reference signal.Type: GrantFiled: February 8, 2013Date of Patent: September 15, 2015Assignee: Excelliance MOS CorporationInventors: Pao-Chuan Lin, Li-Chieh Chen, Hung-Che Chou
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Patent number: 9058043Abstract: A voltage converter includes a constant on time signal generator, a first transistor, a second transistor, an inductor, and a ripple injection circuit. The constant on time signal generator generates a first driving signal and a second driving signal. The ripple injection circuit receives an output signal and generates a ripple injection signal. The constant on time signal generator generates the first and second driving signals according to the ripple injection signal, the output signal, and a reference signal.Type: GrantFiled: March 7, 2013Date of Patent: June 16, 2015Assignee: Excelliance MOS CorporationInventors: Pao-Chuan Lin, Li-Chieh Chen, Hung-Che Chou
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Publication number: 20140253060Abstract: A voltage converter includes a constant on time signal generator, a first transistor, a second transistor, an inductor, and a ripple injection circuit. The constant on time signal generator generates a first driving signal and a second driving signal. The ripple injection circuit receives an output signal and generates a ripple injection signal. The constant on time signal generator generates the first and second driving signals according to the ripple injection signal, the output signal, and a reference signal.Type: ApplicationFiled: March 7, 2013Publication date: September 11, 2014Applicant: Excelliance MOS CorporationInventors: Pao-Chuan Lin, Li-Chieh Chen, Hung-Che Chou
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Publication number: 20140225578Abstract: A voltage converter is disclosed. The voltage converter includes a constant on time signal generator, a first and second transistors, an inductor, a feedback circuit and a ripple injection circuit. The constant on time signal generator generates a first and second driving signals for driving the first and second transistors. The voltage converter generates an output signal at an output end thereof. The feedback circuit divides the output signal to generate a feedback signal at a feedback end of the voltage converter. The ripple injection circuit gets the voltage of the feedback end and the voltage of the phase end to generate a injection signal. The constant on time signal generator generates the first and second driving signals according to the injection signal, the output signal and a reference signal.Type: ApplicationFiled: February 8, 2013Publication date: August 14, 2014Applicant: EXCELLIANCE MOS CORPORATIONInventors: Pao-Chuan Lin, Li-Chieh Chen, Hung-Che Chou