Patents by Inventor Li-Chieh YU
Li-Chieh YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145562Abstract: The present disclosure describes a method to form a backside power rail (BPR) semiconductor device with an air gap. The method includes forming a fin structure on a first side of a substrate, forming a source/drain (S/D) region adjacent to the fin structure, forming a first S/D contact structure on the first side of the substrate and in contact with the S/D region, and forming a capping structure on the first S/D contact structure. The method further includes removing a portion of the first S/D contact structure through the capping structure to form an air gap and forming a second S/D contact structure on a second side of the substrate and in contact with the S/D region. The second side is opposite to the first side.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Zhen YU, Lin-Yu HUANG, Cheng-Chi CHUANG, Chih-Hao WANG, Huan-Chieh SU
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Patent number: 11955515Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.Type: GrantFiled: July 28, 2022Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Chuan Chiu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Yu-Ming Lin
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Patent number: 11955552Abstract: A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a dielectric layer having a continuous surface in contact with the entire second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature. The structure also includes a gate dielectric layer in contact with the continuous surface of the dielectric layer and the second surface of the semiconductor layer, and a gate electrode layer surrounding a portion of the semiconductor layer.Type: GrantFiled: November 14, 2022Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Li-Zhen Yu, Huan-Chieh Su, Shih-Chuan Chiu, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
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Patent number: 11948702Abstract: A radiation source apparatus includes a vessel, a laser source, a collector, a horizontal obscuration bar, and a reflective mirror. The vessel has an exit aperture. The laser source is configured to emit a laser beam to excite a target material to form a plasma. The collector is disposed in the vessel and configured to collect a radiation emitted by the plasma and to reflect the collected radiation to the exit aperture of the vessel. The horizontal obscuration bar extends from a sidewall of the vessel at least to a position between the laser source and the exit aperture of the vessel. The reflective mirror is in the vessel and connected to the horizontal obscuration bar.Type: GrantFiled: May 5, 2023Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Chung Tu, Sheng-Kang Yu, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
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Publication number: 20240096996Abstract: A semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. The dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. The isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Lo-Heng Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 11935794Abstract: A method of forming a semiconductor transistor device. The method comprises forming a channel structure over a substrate and forming a first source/drain structure and a second source/drain structure on opposite sides of the fin structure. The method further comprises forming a gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain structure and the second source/drain structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.Type: GrantFiled: December 12, 2022Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang, Zhi-Chang Lin, Li-Zhen Yu
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Patent number: 11923408Abstract: A semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source/drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a first via disposed under and electrically connected to the first source/drain feature; and a power rail disposed under and electrically connected to the first via.Type: GrantFiled: July 29, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Li-Zhen Yu, Huan-Chieh Su, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
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Patent number: 11915972Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.Type: GrantFiled: July 15, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Zhen Yu, Huan-Chieh Su, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
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Patent number: 10931229Abstract: A solar cell testing system including a lower electrode, a solar cell, an encapsulation material, a sodium-containing template, an upper electrode, a voltage source and a measuring circuit is provided. The solar cell is disposed on the lower electrode. The encapsulation material is disposed on the solar cell. The sodium-containing template is disposed on the encapsulation material, wherein the sodium-containing template has a sodium ion content ranging between 9-39%. The upper electrode is disposed on the sodium-containing template. The voltage source is connected between the upper electrode and the lower electrode. The measuring circuit is connected between the solar cell and the lower electrode for measuring a shunt resistance of the solar cell.Type: GrantFiled: December 13, 2018Date of Patent: February 23, 2021Assignee: Industrial Technology Research InstituteInventors: Li-Chieh Yu, Wei-Lun Yang, Yu-Tai Li, Kuan-Wu Lu, Cho-Fan Hsieh, Ching-Chiao Tsai, San-Yu Ting
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Publication number: 20200195194Abstract: A solar cell testing system including a lower electrode, a solar cell, an encapsulation material, a sodium-containing template, an upper electrode, a voltage source and a measuring circuit is provided. The solar cell is disposed on the lower electrode. The encapsulation material is disposed on the solar cell. The sodium-containing template is disposed on the encapsulation material, wherein the sodium-containing template has a sodium ion content ranging between 9-39%. The upper electrode is disposed on the sodium-containing template. The voltage source is connected between the upper electrode and the lower electrode. The measuring circuit is connected between the solar cell and the lower electrode for measuring a shunt resistance of the solar cell.Type: ApplicationFiled: December 13, 2018Publication date: June 18, 2020Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Li-Chieh YU, Wei-Lun YANG, Yu-Tai LI, Kuan-Wu LU, Cho-Fan Hsieh, Ching-Chiao TSAI, San-Yu TING
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Publication number: 20140012975Abstract: A computer cluster includes a node and a management system. The node includes an agent and generates a node event message in response to occurrence of an event. The agent gathers a software behavior information set, and generates a node information set when the node generates the node event message. The management system is configured to communicate with the node and includes a database storing at least one pre-established solution information set, and an agent management module configured to search the database according to the node information set. Upon finding a solution information set from the database, the agent management module sends the solution information set to the node so that the agent generates a solution for the event.Type: ApplicationFiled: July 9, 2012Publication date: January 9, 2014Applicant: NATIONAL APPLIED RESEARCH LABORATORIESInventors: Ming-Jen WANG, Li-Chieh YU, Chuan-Lin LAI, Chia-Chen KUO, Hsi-Ya CHANG