Patents by Inventor Li-Chien Ting

Li-Chien Ting has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10437567
    Abstract: The present disclosure relates to a computer-implemented method for use in an electronic design environment. Embodiments may include defining, using at least one processor, a grammar object system including one or more of objects, elements, values and relationships. Embodiments may include generating a technology grammar binary representation, based upon, at least in part, the grammar object system and receiving a technology ASCII representation. Embodiments may further include parsing at least one of the technology grammar binary representation and the technology ASCII representation to generate a technology binary representation and providing the technology binary representation to at least one of a graphical user interface or a database.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: October 8, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Li-Chien Ting, Shelly Ann Evans, Serena Chiang Caluya, Alexey Nikolaevich Peskov, Pavel Nikolaevich Migachev, Alexander Smirnov, Oleg Kostyuchenko, David Y. Yang, Roman Vladimirovich Rybalkin
  • Publication number: 20180336017
    Abstract: The present disclosure relates to a computer-implemented method for use in an electronic design environment. Embodiments may include defining, using at least one processor, a grammar object system including one or more of objects, elements, values and relationships. Embodiments may include generating a technology grammar binary representation, based upon, at least in part, the grammar object system and receiving a technology ASCII representation. Embodiments may further include parsing at least one of the technology grammar binary representation and the technology ASCII representation to generate a technology binary representation and providing the technology binary representation to at least one of a graphical user interface or a database.
    Type: Application
    Filed: November 29, 2016
    Publication date: November 22, 2018
    Inventors: Li-Chien Ting, Shellly Ann Evans, Serena Chiang Caluya, Alexey Nikolaevich Peskov, Pavel Nikolarvich Migachev, Alexander Smimov, Oleg Kostyuchenko, David Y Yang, Roman Vladimirovich Rybalkin
  • Patent number: 9336123
    Abstract: A system and method are provided for establishing an automated debugging environment in an Electronic Design Automation (EDA) work flow. A user interface is provided for interfacing with a user by displaying a list of debuggable parameters, accepting a selection thereof from a user, and automatically locating both the callback function which sets the selected parameter, and the source code file which contains the callback function. Additionally, it is determined whether the callback function sets solely the selected parameter, or several different parameters, and an automatic breakpoint is set accordingly to break only responsive to the selected parameter. On execution of the modified callback function, execution will be arrested by the automatically-set intelligent breakpoint and a debugging user interface will be generated and provided to the user with a display of the relevant source code, callback function, parameter names and values, system state, and the like.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: May 10, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Gilles S. C. Lamant, Li-Chien Ting, Serena Chiang Caluya, Chia-Fu Chen
  • Patent number: 9122834
    Abstract: A system, method, and computer program product for using continuous parameter value updates to rapidly evaluate parameterized cells in a design tool. Embodiments display parameters and corresponding parameter values of parameterized cells in a circuit design in a GUI, adjust parameter values according to user input, evaluate the parameterized cell, and present results of the evaluating in the GUI during the displaying. Parameters influence circuit layout, circuit schematics, or simulation settings. Parameter values include current, minimum, maximum, and increment values. Parameterized cells may be individual cell instances, submaster cells, or master cells. Embodiments integrate validation tools and detect design rule check violations, assertion violations, invalid parameter values, and evaluation errors, and responsively generate user error alerts and selectively disallow further adjusting. Embodiments generate test circuits, each using a parameter value from a permutation of the adjusted parameter values.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: September 1, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Serena Chiang Caluya, Li-Chien Ting
  • Patent number: 8726209
    Abstract: A system and method are provided for establishing a debugging environment in an Electronic Design Automation work-flow. A user-interface is provided for interfacing with users by displaying a list of debuggable parameters, accepting a selection thereof, and automatically locating both the callback function which sets the selected parameter, and the source code file which contains the callback function. Additionally, it is determined whether the callback function sets solely the selected parameter, or several different parameters, and an automatic breakpoint is set accordingly to break only responsive to the selected parameter. On execution of the modified callback function, execution will be arrested by the automatically-set intelligent breakpoint and a debugging user-interface will be generated for the user to display the relevant source code, callback function, parameter names and values, system state, and the like. Upon completion of the debugging process, the automatically-set breakpoint will be removed.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: May 13, 2014
    Assignee: C{dot over (a)}dence Design System, Inc.
    Inventors: Gilles S. C. Lamant, Li-Chien Ting, Serena Chiang Caluya, Chia-Fu Chen
  • Patent number: 8719745
    Abstract: A system and method are provided for establishing an automated debugging environment in an Electronic Design Automation (EDA) work flow for the debugging of parameterized cells (PCELLS/PyCELLS) in a layout. A user may merely select a particular PCELL within a hierarchical PCELL and the system and method will determine dependencies thereof. The source code for the selected PCELL and its dependencies may be located and loaded. At least one breakpoint may be set in the source code of the selected PCELL. The source code for the selected PCELL and its dependencies may be executed to be arrested at the set breakpoints. Upon the arrest of execution, a debugging environment may be established and the located source code of the selected PCELL may be displayed along with values for parametric components thereof and progression control tools.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: May 6, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Li-Chien Ting, Nikolay Vladimirovich Anufriev, Alexey Nikolayevich Peskov, Serena Chiang Caluya, Chia-Fu Chen
  • Publication number: 20130298092
    Abstract: A system and method are provided for establishing an automated debugging environment in an Electronic Design Automation (EDA) work flow for the debugging of parameterized cells (PCELLS/PyCELLS) in a layout. A user may merely select a particular PCELL within a hierarchical PCELL and the system and method will determine dependencies thereof. The source code for the selected PCELL and its dependencies may be located and loaded. At least one breakpoint may be set in the source code of the selected PCELL. The source code for the selected PCELL and its dependencies may be executed to be arrested at the set breakpoints. Upon the arrest of execution, a debugging environment may be established and the located source code of the selected PCELL may be displayed along with values for parametric components thereof and progression control tools.
    Type: Application
    Filed: November 27, 2012
    Publication date: November 7, 2013
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: LI-CHIEN TING, NIKOLAY VLADIMIROVICH ANUFRIEV, ALEXEY NIKOLAYEVICH PESKOV, SERENA CHIANG CALUYA, CHIA-FU CHEN
  • Patent number: 8560109
    Abstract: Various embodiments of the present invention relate to bi-directional communication between an Integrated Circuit (IC) layout editor and various generic layout and/or pattern data viewers. Further, the present invention provides a bi-directional control between the IC layout editor and the various generic layout and/or pattern data viewers and allows substantially simultaneous display of an IC design in various IC mask layout data formats. The IC layout editor and the various generic layout and/or pattern data viewers include various tools. The bi-directional communication connects these tools to form connected tools. Subsequently, the actions performed by a connected tool in response to user interactions are synchronized with the actions performed by other connected tools.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: October 15, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Aaron A. Parr, Rodney Rigby, Cody Kyrobie, Li-Chien Ting