Abstract: An electronic device with a plurality of booting modes comprises at least a button unit, a control module, a control chip unit, a super I/O unit and a Basic Input/Output System (BIOS). One of the button units outputs a first signal according to a trigger event. The control module includes a buffer unit connected to the button units. The control module sets the buffer unit according to the first signal. The control module outputs a status signal and copies the first signal and outputs the first signal after a delay time. The control chip unit receives the status signal. The super I/O unit receives the first signal outputted from the control module and transmits the first signal to the control chip unit. When the control chip unit receives the status signal and the first signal, the BIOS executes the corresponding booting procedure according to the status signal.

Abstract: A computer device and a method for converting a working mode of a universal serial bus (USB) connector of the computer device. The computer device comprises a USB connector, a power interruption unit, a first switch unit, a south bridge chip, a reading unit, a control unit, and a charging control unit. The USB connector is linked to an external USB device. When a fast charging instruction is received, the power interruption unit interrupts the power supply of the USB connector; the first switch unit performs switching, so that the USB connector works in a fast charging mode. When the control unit receives a common charging instruction, the power interruption unit interrupts the power supply of the USB connector; the first switch unit performs switching, so that the USB connector works in a common charging mode, and data transmission can be performed.

Abstract: A computer device and a method for converting a working mode of a universal serial bus (USB) connector of the computer device. The computer device comprises a USB connector, a power interruption unit, a first switch unit, a south bridge chip, a reading unit, a control unit, and a charging control unit. The USB connector is linked to an external USB device. When a fast charging instruction is received, the power interruption unit interrupts the power supply of the USB connector; the first switch unit performs switching, so that the USB connector works in a fast charging mode. When the control unit receives a common charging instruction, the power interruption unit interrupts the power supply of the USB connector; the first switch unit performs switching, so that the USB connector works in a common charging mode, and data transmission can be performed.

Abstract: A computer device and frequency adjusting method for central processing unit are provided. The computer device including a CPU, a voltage regulator module, a clock generator, a power-on module, a chip set and an embedded controller. The power-on module activates the voltage regulator module, the clock generator and the CPU respectively. The voltage regulator module provides the operating voltage of the CPU. The clock generator provides the operating clock of the CPU. Before the CPU is activated, the embedded controller adjusts the operating clock and the operating voltage provided from the clock generator and the voltage regulator module the CPU, the CPU performs overclocking/downclocking directly by using the adjusted operating clock and the adjusted operating voltage after the CPU is activated.

Abstract: An electronic device includes a circuit board, a connector and an electronic module. The connector includes an insulating body and a first terminal set. The insulating body includes a concave. The first terminal set is fastened on the insulating body and is electrically connected to the circuit board. The electronic module is detachably disposed in the concave and includes a second terminal set. The second terminal set contacts the first terminal set to be electrically connected to the circuit board.

Abstract: An electronic device with a plurality of booting modes comprises at least a button unit, a control module, a control chip unit, a super I/O unit and a Basic Input/Output System (BIOS). One of the button units outputs a first signal according to a trigger event. The control module includes a buffer unit connected to the button units. The control module sets the buffer unit according to the first signal. The control module outputs a status signal and copies the first signal and outputs the first signal after a delay time. The control chip unit receives the status signal. The super I/O unit receives the first signal outputted from the control module and transmits the first signal to the control chip unit. When the control chip unit receives the status signal and the first signal, the BIOS executes the corresponding booting procedure according to the status signal.

Abstract: A transmission interface system includes a connector; a detecting unit, a control unit, a chipset and a resetting unit. The connector includes lots of transmission interfaces. The detecting unit detects the data type of the current transmitting data and outputs a detecting signal; the control unit receives the detecting signal and informs the resetting unit to output a resetting signal to the chipset. The chipset is reset after receiving the resetting signal, and then the control unit informs the chipset to output a data signal corresponding to the data type of the current transmitting data to the connector.

Abstract: A signal switch connector set is disposed on a motherboard of a computer system. The signal switch connector set is capable of selectively connecting a USB 3.0 signal terminal of a south bridge chip to a USB 3.0 port located at the rear panel of a casing or connecting the USB 3.0 terminal of the south bridge chip to the USB 3.0 port located at the front panel of the casing.

Abstract: A system management bus (SM Bus) system includes an arbitrator; a slave device connected to the arbitrator via an SM Bus; a first master device connected to the arbitrator capable of sending a first start command for communicating with the slave device; and a second master device connected to the arbitrator capable of sending a second start command for communicating with the slave device. The arbitrator set the first master device to have a priority, and when the first start command is being executed and the arbitrator receives the second start command, the arbitrator confirms whether the SM Bus is busy or not after a second predetermined time, and if the SM Bus is not busy, the arbitrator transmits the second start command to the slave devices via the SM Bus.

Abstract: A computer device and frequency adjusting method for central processing unit are provided. The computer device including a CPU, a voltage regulator module, a clock generator, a power-on module, a chip set and an embedded controller. The power-on module activates the voltage regulator module, the clock generator and the CPU respectively. The voltage regulator module provides the operating voltage of the CPU. The clock generator provides the operating clock of the CPU. Before the CPU is activated, the embedded controller adjusts the operating clock and the operating voltage provided from the clock generator and the voltage regulator module the CPU, the CPU performs overclocking/downclocking directly by using the adjusted operating clock and the adjusted operating voltage after the CPU is activated.

Abstract: An overclocking control method cooperates with an overclocking application of a computer system when the overclocking application is started. The overclocking control method includes the steps as follows. A BIOS enters an overclocking mode according to an executing state of the overclocking application. The BIOS receives a first triggering signal outputted from a south bridge chip, and the first triggering signal is generated by the south bridge chip according to a first button of the computer system. The BIOS selects a piece of corresponding overclocking information from a look-up table and loads the overclocking information into a register of the BIOS according to the first triggering signal to control the overclocking of the computer system.

Abstract: A computer system and a monitoring device for a computer system are disclosed. The computer system includes a plurality of electronic modules, a memory module and an embedded controller. The embedded controller is coupled to the electronic modules and the memory module, respectively. The embedded controller collects information of the electronic modules and generates the system information about the electronic modules. The embedded controller selectively writes the system information into the memory module. The system information in the memory module can be provided to the user or the maintenance engineer for system analysis. Besides, the computer system may utilize an application program to monitor the system information, so as to achieve the error prevention and alert function.

Abstract: An electronic device includes a circuit board, a connector and an electronic module. The connector includes an insulating body and a first terminal set. The insulating body includes a concave. The first terminal set is fastened on the insulating body and is electrically connected to the circuit board. The electronic module is detachably disposed in the concave and includes a second terminal set. The second terminal set contacts the first terminal set to be electrically connected to the circuit board.

Abstract: A connector is disposed at a circuit board and utilized for connecting to an external connecting port which is detachably connected to the connector of the circuit board via a connecting terminal, so as to provide an expansion connecting channel between the connecting port and the circuit board. The connector includes the plurality of power pins and the plurality of signal pins, and the length of the power pins is longer than that of the signal pins along an assembling direction of the connecting terminal to the connector. Thus, when the connecting terminal is removed from the connector, the connecting terminal is detached from the connecting pins first to stop the data transmission to avoid the data loss or damage due to the power off, thus to achieve the “hot-plug” function, and also to avoid the damage of the host or the external device.

Abstract: A control circuit of universal serial bus (USB) port includes a charge control unit providing a first operating voltage and a second operating voltage to a first operating voltage end and a second operating voltage end of the USB port, and a first circuit unit coupled to the charge control unit. Furthermore, the first circuit includes a first output end and a second output end. When a external apparatus is inserted into the USB port, the charge control unit connects the first output end and the second output end to a differential positive end and a differential negative end of the USB port, respectively, to enter a rapid charging mode.

Abstract: A signal switch connector set is disposed on a motherboard of a computer system. The signal switch connector set is capable of selectively connecting a USB 3.0 signal terminal of a south bridge chip to a USB 3.0 port located at the rear panel of a casing or connecting the USB 3.0 terminal of the south bridge chip to the USB 3.0 port located at the front panel of the casing.

Abstract: A motherboard including a bus connector and a printed circuit board (PCB) is provided. The bus connector includes a plurality of pins, and each of the pins further includes a first end and a second end. The PCB includes a plurality of contact pads. The second ends of the pins are electrically connected to the contact pads of the PCB via a surface mounted technology (SMT), respectively.

Abstract: A computer system is provided and it is capable of communicating with a blue-tooth device. The computer system includes a blue-tooth chipset which stores a media access control (MAC) address of the computer system and the blue-tooth device; and a power management system electrically connected to the blue-tooth chipset. When the blue-tooth device is out of a detectable coverage and the computer system is in a power saving mode, the blue-tooth chipset outputs a first control signal to make the power management system change the power saving mode of the computer system, if the blue-tooth device is detected in the detectable coverage.

Abstract: A system management bus (SM Bus) system includes an arbitrator; a slave device connected to the arbitrator via an SM Bus; a first master device connected to the arbitrator capable of sending a first start command for communicating with the slave device; and a second master device connected to the arbitrator capable of sending a second start command for communicating with the slave device. The arbitrator set the first master device to have a priority, and when the first start command is being executed and the arbitrator receives the second start command, the arbitrator confirms whether the SM Bus is busy or not after a second predetermined time, and if the SM Bus is not busy, the arbitrator transmits the second start command to the slave devices via the SM Bus.

Abstract: A computer system and a monitoring device for a computer system are disclosed. The computer system includes a plurality of electronic modules, a memory module and an embedded controller. The embedded controller is coupled to the electronic modules and the memory module, respectively. The embedded controller collects information of the electronic modules and generates the system information about the electronic modules. The embedded controller selectively writes the system information into the memory module. The system information in the memory module can be provided to the user or the maintenance engineer for system analysis. Besides, the computer system may utilize an application program to monitor the system information, so as to achieve the error prevention and alert function.