Abstract: An adaptive control method based on an input clock includes: performing a read process according to the input clock; receiving a read command; receiving a data signal via a data line according to the read command; enabling an amplifier element according to at least the input clock; and utilizing the amplifier element to amplify the data signal.

Abstract: A high speed test circuit receives a tester clock from a tester and it conducts a test on a circuit under test. The high speed test circuit generates a high frequency clock according to the tester clock, so it is capable of operating in two frequencies. The high speed test circuit tests the circuit under test according to the high frequency clock, and it performs a low speed operation according to a low frequency clock, which is for example the tester clock.

Abstract: A high speed test circuit receives a tester clock from a tester and it conducts a test on a circuit under test. The high speed test circuit generates a high frequency clock according to the tester clock, so it is capable of operating in two frequencies. The high speed test circuit tests the circuit under test according to the high frequency clock, and it performs a low speed operation according to a low frequency clock, which is for example the tester clock.

Abstract: A particular wide band interface circuit provides an interface between a very fast slope clock signal input and a very slow slope voltage controlled delay cell of a delay lock loop. The invention generates the internal clock signal to track the slope of each delay stage, whether it is a higher frequency for which the slope of the delay stage is faster or a lower frequency for which the slope of the delay stage is slower. The integrated circuit includes a voltage bias portion, an analog clock input portion, circuit devices for interfacing with clock frequency inputs over all the available frequency range, and an output portion for producing clock signals. The invention applies to the multiple delay stages of a delay lock loop.

Abstract: A dual phase synchronous race delay clock circuit that will create an internal clock signal in an integrated circuit that is synchronized with and has minimum skew from an external system clock signal is disclosed. The synchronous race delay circuit has an input buffer circuit to receive, buffer, and amplify an external clock signal. The input buffer circuit has a delay time that is the first delay time. A fast pulse generator is connected to the input buffer circuit to create a fast pulse signal. The fast pulse generator is connected to a slow pulse generator to create a slow pulse signal. The fast pulse generator and the slow pulse generator is connected to a race delay measurement means to determine a measurement of a period of the external system clock by comparing a time difference between the slow pulse signal and a following fast pulse signal. A delay control means is connected to the race delay measurement means to receive the measurement of the period of the external system clock.

Abstract: A multiple phase latched type synchronized clock circuit that will create a multiple phases of an internal clock signal in an integrated circuit that is synchronized with an external system clock signal is disclosed. A latched type clock synchronizer circuit has an input buffer circuit to receive the external input clock to create a first timing clock. The input buffer is connected to a delay monitor circuit to delay the first timing clock by a first delay factor to create a second timing clock. A delay measurement latch array is connected to the input buffer circuit and the delay monitor circuit to create a latched measurement signal, which indicates a period of time between a second pulse of the first timing clock and a first pulse of the second timing clock. A multiple delay array is connected to the input buffer to receive the first timing clock and will create multiple pluralities of incrementally delayed timing clocks.