Abstract: The invention relates to an ultra-lightweight heat and flame resistant (or retardant) composite panel having a three-dimensional artistic design on the surface, and a method for making the lightweight heat and flame resistant composite panel. One aspect of the invention is a system and method for creating a composite panel from high performance heat and flame resistant materials, such as aramid polyamide polymers (for example, NOMEX® from DuPont) or any other fire-retardant or fire-retardant treated material, which can be bonded to another layer of fire-retardant material such as paper, fabric, honeycomb or foam. The fire-retardant materials can be bonded by a welding machine such as an ultrasonic machine, or attached by a thermoplastic, thermoset, thermobond or other fire resistant adhesive. The thickness of the finished composite may be around 1/16˜¼ inch.

Abstract: A ring-type signal controlled oscillator comprising a series of active delay elements, each including a respective differential pair of transistors. The inputs and outputs of the differential pair transistors are interconnected in a closed ring to produce oscillations at a frequency determined by the delay of each delay element. The differential pair of transistors further has a pair of current source inputs for controlling an amount of delay of the delay element, and a pair of load inputs for stabilizing the amount of delay. The invention advantageously provides high frequency operation with substantially symmetric rise and fall time, while limiting spread in oscillation frequency and spread in amplitude in relation to fabrication process variability and power supply variability.

Abstract: A test coverage tool determines the adequacy of a set of test vectors for a state simulator for exercising logic paths in a logic circuit design. The speed coverage tool generally compares state data from a state simulator and timing data from a timing simulator in order to validate whether a test vector covers a simulated timing path. In architecture, the speed coverage tool includes first logic configured to acquire state data from the logic circuit design that has been produced by a state simulator based upon test vectors. Second logic associated with the tool obtains timing data concerning one or more logic paths of the logic circuit design that has been produced using a timing simulator. Third logic associated with the test coverage tool is configured to determine a transition score by comparing the timing data with the state data. The score is indicative of the adequacy of a set of test vectors.

Abstract: An analog, fully integrated, partial response maximum likelihood (PRML) read channel utilizing a high-performance analog delay line, an analog adaptive equalizer and an analog Viterbi detector is provided, resulting in saved space, performance gains, and lower power consumption. For signal detection and reconstruction used in read operations, the partial response maximum likelihood (PRML) read channel includes a variable gain amplifier coupled to a lowpass filter for input to an adaptive analog equalizer. The adaptive analog equalizer comprises an analog delay line and an analog feedforward equalizer (FFE). An analog Viterbi detector employs maximum-likelihood sequence estimation (MLSE) techniques to performs the signal detection function. A decoder/descrambler produces a final reconstructed signal. The analog implementation of a partial response maximum likelihood (PRML) read channel also includes a scrambler/encoder coupled to a write precompensation circuit for output to a separate write head.

Abstract: A dual adjust current-controlled phase locked loop is provided for allowing multiple-gain frequency acquisition of a signal. The dual adjust current-controlled phase locked loop includes a phase detector responsive to a reference signal and a synthesized signal for producing a phase error signal; a controller responsive to the phase error signal for generating coarse and fine adjust control signals; and a dual adjust current-controlled oscillator responsive to the coarse and fine adjust control signals for adjusting the oscillating frequency of the synthesized signal. The dual adjust current controlled oscillator includes a differential current controlled ring oscillator comprising a series of delay elements. Each delay element includes a high gain circuit responsive to the coarse adjust control signal and a low gain circuit responsive to the fine adjust control signal.