Abstract: Provided is a probe card, comprising a guide plate and a shielding structure of single-layer or multi-layer. The guide plate comprises an upper surface, a lower surface, and at least one guide hole passing through the upper surface and the lower surface, and the guide hole is provided with an inner wall surface. At least one layer of the shielding structure is made of an electromagnetic absorption material or an electromagnetic reflection material, and the shielding structure is not connected to a ground. Each layer of the shielding structure is formed on the inner wall surface of the guide hole by means of atomic layer deposition or atomic layer etching, and a thickness of each layer is less than 1000 nm.

Abstract: A substrate structure includes at least one detachable first substrate unit and a substrate body. The detachable first substrate unit includes a plurality of corners and a plurality of first engagement portions. Each of the first engagement portions is disposed at each of the corners of the detachable first substrate unit. The substrate body includes a plurality of second substrate units, at least one opening and a plurality of second engagement portions. The opening is substantially defined by a plurality of sidewalls of the second substrate units, and includes a plurality of corners. Each of the second engagement portions is disposed at each of the corners of the opening. The detachable first substrate unit is disposed in the opening, and the second engagement portions are engaged with the first engagement portions.

Abstract: A semiconductor substrate includes a multi-layered structure, a component and a first conductive via. The multi-layered structure includes a plurality of dielectric layers and a plurality of patterned conductive layers. A topmost patterned conductive layer of the patterned conductive layers is embedded in a topmost dielectric layer of the dielectric layers. The component is embedded in the multi-layered structure. The first conductive via is electrically connected to the component and one of the patterned conductive layers.

Abstract: A semiconductor package includes a semiconductor substrate structure, a semiconductor die and an encapsulant. The semiconductor substrate structure includes a dielectric structure, a first patterned conductive layer, a first insulation layer and a conductive post. The first patterned conductive layer is embedded in the dielectric structure. The first insulation layer is disposed on the dielectric structure. The conductive post connects to the first patterned conductive layer and protrudes from the first insulation layer. The first insulation layer has a greater thickness at a position closer to the conductive post. The semiconductor die is electrically connected to the conductive post. The encapsulant covers the semiconductor die and at least a portion of the semiconductor substrate structure.

Abstract: A semiconductor package includes a semiconductor substrate structure, a semiconductor die and an encapsulant. The semiconductor substrate structure includes a dielectric structure, a first patterned conductive layer, a first insulation layer and a conductive post. The first patterned conductive layer is embedded in the dielectric structure. The first insulation layer is disposed on the dielectric structure. The conductive post connects to the first patterned conductive layer and protrudes from the first insulation layer. The first insulation layer has a greater thickness at a position closer to the conductive post. The semiconductor die is electrically connected to the conductive post. The encapsulant covers the semiconductor die and at least a portion of the semiconductor substrate structure.

Abstract: A substrate structure includes at least one detachable first substrate unit and a substrate body. The detachable first substrate unit includes a plurality of corners and a plurality of first engagement portions. Each of the first engagement portions is disposed at each of the corners of the detachable first substrate unit. The substrate body includes a plurality of second substrate units, at least one opening and a plurality of second engagement portions. The opening is substantially defined by a plurality of sidewalls of the second substrate units, and includes a plurality of corners. Each of the second engagement portions is disposed at each of the corners of the opening. The detachable first substrate unit is disposed in the opening, and the second engagement portions are engaged with the first engagement portions.

Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure, a dielectric structure and a metal bump. The conductive structure has a first conductive surface and a second conductive surface. The dielectric structure has a first dielectric surface and a second dielectric surface. The first conductive surface does not protrude from the first dielectric surface. The second conductive surface is recessed from the second dielectric surface. The metal bump is disposed in a dielectric opening of the dielectric structure, and is physically and electrically connected to the second conductive surface. The metal bump has a concave surface.

Abstract: The present disclosure relates to a package substrate. The package substrate includes a patterned conductive layer and conductive pillars. Each of the conductive pillars includes a first portion and a second portion, where the first portion contacts the patterned conductive layer at one end of the first portion, and the second portion is adjacent to another end of the first portion. A thickness of the first portion is greater than a thickness of the second portion. Side surfaces of the first portion are substantially coplanar to side surfaces of the second portion.

Abstract: A semiconductor substrate includes a first dielectric layer, a first patterned conductive layer disposed in the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, and a first bump pad disposed in the second dielectric layer. The first bump pad is electrically connected to the first patterned conductive layer, and the first bump pad has a curved surface surrounded by the second dielectric layer.

Abstract: At least some embodiments of the present disclosure relate to a substrate for packaging a semiconductor device. The substrate includes a first dielectric layer having a first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, and a conductive post. The first patterned conductive layer includes a first conductive pad and a second conductive pad. The conductive post is disposed on the first conductive pad. The conductive post includes a first portion and a second portion. The first portion and the second portion of the conductive post are exposed by the first dielectric layer. The first portion of the conductive post has a first width corresponding to a top line width of the first portion and the second portion of the conductive post has a width. The width of the second portion of the conductive post is greater than the first width of the first portion of the conductive post.

Abstract: A semiconductor substrate includes a first dielectric layer, a first patterned conductive layer disposed in the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, and a first bump pad disposed in the second dielectric layer. The first bump pad is electrically connected to the first patterned conductive layer, and the first bump pad has a curved surface surrounded by the second dielectric layer.

Abstract: At least some embodiments of the present disclosure relate to a substrate for packaging a semiconductor device. The substrate includes a first dielectric layer having a first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, and a conductive post. The first patterned conductive layer includes a first conductive pad and a second conductive pad. The conductive post is disposed on the first conductive pad. The conductive post includes a first portion and a second portion. The first portion and the second portion of the conductive post are exposed by the first dielectric layer. The first portion of the conductive post has a first width corresponding to a top line width of the first portion and the second portion of the conductive post has a width. The width of the second portion of the conductive post is greater than the first width of the first portion of the conductive post.

Abstract: A substrate includes a dielectric layer having a first surface and a second surface opposite to the first surface, a first circuit layer and at least one second conductive element. The first circuit layer is disposed adjacent to the first surface of the dielectric layer, and includes at least one trace and at least one first conductive element connected to the trace. The first conductive element does not extend through the dielectric layer. The second conductive element extends through the dielectric layer. An area of an upper surface of the second conductive element is substantially equal to an area of an upper surface of the first conductive element.

Abstract: A semiconductor substrate includes a multi-layered structure, a component and a first conductive via. The multi-layered structure includes a plurality of dielectric layers and a plurality of patterned conductive layers. A topmost patterned conductive layer of the patterned conductive layers is embedded in a topmost dielectric layer of the dielectric layers. The component is embedded in the multi-layered structure. The first conductive via is electrically connected to the component and one of the patterned conductive layers.

Abstract: A semiconductor package includes a semiconductor substrate structure, a semiconductor die and an encapsulant. The semiconductor substrate structure includes a dielectric structure, a first patterned conductive layer, a first insulation layer and a conductive post. The first patterned conductive layer is embedded in the dielectric structure. The first insulation layer is disposed on the dielectric structure. The conductive post connects to the first patterned conductive layer and protrudes from the first insulation layer. The first insulation layer has a greater thickness at a position closer to the conductive post. The semiconductor die is electrically connected to the conductive post. The encapsulant covers the semiconductor die and at least a portion of the semiconductor substrate structure.

Abstract: A semiconductor substrate includes: (1) a first dielectric structure having a first surface and a second surface opposite the first surface; (2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; (3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and (4) a second patterned conductive layer, disposed on and contacting the second surface of the first dielectric structure and including at least one conductive trace, wherein the first dielectric structure defines at least one opening, and a periphery of the opening corresponds to a periphery of the through hole of the second dielectric structure.

Abstract: A package structure includes a carrier defining a cavity in which a die is disposed. A dielectric material fills the cavity around the die. A first conductive layer is disposed over a first surface of the carrier. A first dielectric layer is disposed over an active surface of the die, the first conductive layer and the first surface of the carrier. A first conductive pattern is disposed over the first dielectric layer, and is electrically connected to the first conductive layer and to the active surface of the die. A second dielectric layer is disposed over the second surface of the carrier and defines a hole having a wall aligned with a sidewall of the cavity. A second conductive layer is disposed over the second dielectric layer. A third conductive layer is disposed on the sidewall of the cavity and the wall of the second dielectric layer.

Abstract: A semiconductor substrate includes: (1) a first dielectric structure having a first surface and a second surface opposite the first surface; (2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; (3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and (4) a second patterned conductive layer, disposed on and contacting the second surface of the first dielectric structure and including at least one conductive trace, wherein the first dielectric structure defines at least one opening, and a periphery of the opening corresponds to a periphery of the through hole of the second dielectric structure.

Abstract: A substrate includes a dielectric layer having a first surface and a second surface opposite to the first surface, a first circuit layer and at least one second conductive element. The first circuit layer is disposed adjacent to the first surface of the dielectric layer, and includes at least one trace and at least one first conductive element connected to the trace. The first conductive element does not extend through the dielectric layer. The second conductive element extends through the dielectric layer. An area of an upper surface of the second conductive element is substantially equal to an area of an upper surface of the first conductive element.

Abstract: The present disclosure relates to a package substrate. The package substrate includes a patterned conductive layer and conductive pillars. Each of the conductive pillars includes a first portion and a second portion, where the first portion contacts the patterned conductive layer at one end of the first portion, and the second portion is adjacent to another end of the first portion. A thickness of the first portion is greater than a thickness of the second portion. Side surfaces of the first portion are substantially coplanar to side surfaces of the second portion.