Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer.

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

Abstract: A method for manufacturing an extra low-k (ELK) inter-metal dielectric (IMD) layer includes forming a first IMD layer including a plurality of dielectric material layers over a substrate. An adhesion layer is formed over the first IMD layer. An ELK dielectric layer is formed over the adhesion layer. A protection layer is formed over the ELK dielectric layer. A hard mask is formed over the protection layer and is patterned to create a window. Layers underneath the window are removed to create an opening. The removed layers include the protection layer, the ELK dielectric layer, the adhesion layer, and the first IMD layer. A metal layer is formed in the opening.

Abstract: A method for manufacturing an extra low-k (ELK) inter-metal dielectric (IMD) layer includes forming a first IMD layer including a plurality of dielectric material layers over a substrate. An adhesion layer is formed over the first IMD layer. An ELK dielectric layer is formed over the adhesion layer. A protection layer is formed over the ELK dielectric layer. A hard mask is formed over the protection layer and is patterned to create a window. Layers underneath the window are removed to create an opening. The removed layers include the protection layer, the ELK dielectric layer, the adhesion layer, and the first IMD layer. A metal layer is formed in the opening.

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

Abstract: Embodiments described herein relate generally to methods for forming low-k dielectrics and the structures formed thereby. In some embodiments, a dielectric is formed over a semiconductor substrate. The dielectric has a k-value equal to or less than 3.9. Forming the dielectric includes using a plasma enhanced chemical vapor deposition (PECVD). The PECVD includes flowing a diethoxymethylsilane (mDEOS, C5H14O2Si) precursor gas, flowing an oxygen (O2) precursor gas; and flowing a carrier gas. A ratio of a flow rate of the mDEOS precursor gas to a flow rate of the carrier gas is less than or equal to 0.2.

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

Abstract: Embodiments described herein relate generally to methods for forming low-k dielectrics and the structures formed thereby. In some embodiments, a dielectric is formed over a semiconductor substrate. The dielectric has a k-value equal to or less than 3.9. Forming the dielectric includes using a plasma enhanced chemical vapor deposition (PECVD). The PECVD includes flowing a diethoxymethylsilane (mDEOS, C5H14O2Si) precursor gas, flowing an oxygen (O2) precursor gas; and flowing a carrier gas. A ratio of a flow rate of the mDEOS precursor gas to a flow rate of the carrier gas is less than or equal to 0.2.

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

Abstract: Embodiments described herein relate generally to methods for forming low-k dielectrics and the structures formed thereby. In some embodiments, a dielectric is formed over a semiconductor substrate. The dielectric has a k-value equal to or less than 3.9. Forming the dielectric includes using a plasma enhanced chemical vapor deposition (PECVD). The PECVD includes flowing a diethoxymethylsilane (mDEOS, C5H14O2Si) precursor gas, flowing an oxygen (O2) precursor gas; and flowing a carrier gas. A ratio of a flow rate of the mDEOS precursor gas to a flow rate of the carrier gas is less than or equal to 0.2.

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

Abstract: A method for manufacturing an extra low-k (ELK) inter-metal dielectric (IMD) layer includes forming a first IMD layer including a plurality of dielectric material layers over a substrate. An adhesion layer is formed over the first IMD layer. An ELK dielectric layer is formed over the adhesion layer. A protection layer is formed over the ELK dielectric layer. A hard mask is formed over the protection layer and is patterned to create a window. Layers underneath the window are removed to create an opening. The removed layers include the protection layer, the ELK dielectric layer, the adhesion layer, and the first IMD layer. A metal layer is formed in the opening.

Abstract: A method for manufacturing an extra low-k (ELK) inter-metal dielectric (IMD) layer includes forming a first IMD layer including a plurality of dielectric material layers over a substrate. An adhesion layer is formed over the first IMD layer. An ELK dielectric layer is formed over the adhesion layer. A protection layer is formed over the ELK dielectric layer. A hard mask is formed over the protection layer and is patterned to create a window. Layers underneath the window are removed to create an opening. The removed layers include the protection layer, the ELK dielectric layer, the adhesion layer, and the first IMD layer. A metal layer is formed in the opening.

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

Abstract: Embodiments described herein relate generally to methods for forming low-k dielectrics and the structures formed thereby. In some embodiments, a dielectric is formed over a semiconductor substrate. The dielectric has a k-value equal to or less than 3.9. Forming the dielectric includes using a plasma enhanced chemical vapor deposition (PECVD). The PECVD includes flowing a diethoxymethylsilane (mDEOS, C5H14O2Si) precursor gas, flowing an oxygen (O2) precursor gas; and flowing a carrier gas. A ratio of a flow rate of the mDEOS precursor gas to a flow rate of the carrier gas is less than or equal to 0.2.

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.