Abstract: A device including a first vertical field effect transistor having a first drain/source region and a second drain/source region, and a second vertical field effect transistor having a third drain/source region and a fourth drain/source region. The device including a first power contact situated on a frontside of the device and coupled to the first drain/source region, a second power contact situated on the frontside of the device and coupled to the third drain/source region, and a contact situated on a backside of the device and coupled to the second drain/source region and to the fourth drain/source region.

Abstract: A semiconductor device includes a transistor layer, a first via layer over the transistor layer, a first metallization layer over the first via layer, the first metallization layer including first conductors having long axes extending substantially in a first direction, a second via layer over the first metallization layer, and a conductive deep via extending in the second via layer, the first metallization layer, and the first via layer. The first conductors represent a majority of conductive material in the first metallization layer, and a size of the deep via in the first direction in the first metallization layer is substantially less than a minimum length of the first conductors in the first metallization layer.

Abstract: A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.

Abstract: A semiconductor device includes a semiconductor substrate with active regions and a first buried metal layer provided below the semiconductor substrate. The first buried metal layer includes a first buried conductive rail, a first set of buried conductive fingers that extends from the first buried conductive rail, and a second set of buried conductive fingers that are interleaved with the first set of buried conductive fingers. The first set and the second set of buried conductive fingers extends beneath more than one of the active regions. In this manner, the first set and the second set of buried conductive fingers can be utilized to distribute different voltages, such as an ungated reference voltage TVDD and a gated reference voltage VVDD in a header circuit with reduced resistance.

Abstract: A method of manufacturing an ECO base cell includes forming first and second active areas on opposite sides of, and having corresponding long axes arranged parallel to, a first axis of symmetry; forming non-overlapping first, second and third conductive structures having long axes in a second direction perpendicular to the first direction and parallel to a second axis of symmetry, each of the first, second and third conductive structures to correspondingly overlap the first and second active areas, the first conductive structure being between the second and third conductive structures; removing material from central regions of the second and third conductive structures; and forming a fourth conductive structure being over the central regions of the second and third conductive structures and occupying an area which substantially overlaps a first segment of the first conductive structure and a first segment of one of the second and third conductive structures.

Abstract: An integrated circuit includes a first-type active-region structure and a second-type active-region structure extending in a first direction and a first terminal-conductor and a second terminal-conductor extending in a second direction. The integrated circuit also includes a first power stub and a second power stub in a first metal layer and a first power line and a second power line in a second metal layer. The integrated circuit further includes a first via connector directly connected between the first power stub and the first terminal-conductor, a second via connector directly connected between the second power stub and the second terminal-conductor, a third via connector directly connected between the first power stub and the first power line, and a fourth via connector directly connected between the second power stub and the second power line.

Abstract: A semiconductor device includes: fins configured to include: first active fins having a first conductivity type; and second active fins having a second conductivity type; and at least one gate structure formed over corresponding ones of the fins; and wherein the fins and the at least one gate structure are located in at least one cell region; and each cell region, relative to the second direction, including: a first active region which includes a sequence of three or more consecutive first active fins located in a central portion of the cell region; a second active region which includes one or more second active fins located between the first active region and a first edge of the cell region; and a third active region which includes one or more second active fins located between the first active region and a second edge of the cell region.

Abstract: A semiconductor device, includes a first metal layer, a second metal layer, a drain/source contact and at least one conductive via. The first metal layer has a first conductor that extends in a first direction and a second conductor that extends in the first direction, wherein the second conductor is directly adjacent to the first conductor. The second metal layer has a third conductor that extends in a second direction, wherein the second direction is transverse to the first direction. The drain/source contact extends in the second direction and is connected to the second conductor. The at least one conductive via connects the first conductor and the second conductor through the third conductor.

Abstract: A transmission gate structure includes first and second PMOS transistors positioned in a first active area, first and second NMOS transistors positioned in a second active area parallel to the first active area, and four metal segments parallel to the active areas. A first metal segment overlies the first active area, a fourth metal segment overlies the second active area, and second and third metal segments are a total of two metal segments positioned between the first and fourth metal segments. A first conductive path connects gates of the first PMOS and NMOS transistors, a second conductive path connects gates of the second PMOS and NMOS transistors, a third conductive path connects a source/drain (S/D) terminal of each of the first and second PMOS transistors and first and second NMOS transistors and includes a first conductive segment extending across at least three of the four metal segments.

Abstract: A method of generating a layout diagram of a semiconductor device includes populating a conductive layer M(h) with segment patterns representing corresponding conductive segments in the semiconductor device. The segment patterns including first and second power grid (PG) patterns and first routing patterns, where h is an integer and h?1. Arranging long axes of the first and second PG patterns and the first routing patterns to extend in a first direction. Arranging the first and second PG patterns to be separated, relative to a second direction, by a PG gap having a midpoint. The second direction being substantially perpendicular to the first direction. Distributing the first routing patterns between the first and second PG patterns and substantially uniformly in the second direction with respect to the midpoint of the PG gap.

Abstract: A method includes forming, over a substrate, adjacent first and second transistor stacks each including a first transistor, and a second transistor over the first transistor. A plurality of first conductive lines is formed in a first metal layer. The plurality of first conductive lines includes a power conductive line configured to route power to the first transistor stack, one or more signal conductive lines configured to route one or more signals to the first transistor stack, and a shielding conductive line configured to shield the routed one or more signals. The power conductive line or the shielding conductive line is shared with the second transistor stack.

Abstract: A method includes fabricating a first-type active-region semiconductor structure and second-type active-region semiconductor structure stacked with each other. The method also includes fabricating an upper source conductive segment intersecting the second-type active-region semiconductor structure at a second source region and forming a front-side power rail extending in a first direction that is conductively connected to the upper source conductive segment through a front-side terminal via-connector. The method further includes forming a top-to-bottom via-connector that passes through the substrate and conductively connects to the upper source conductive segment, forming a back-side metal layer on a backside of the substrate, and forming a back-side power node extending in the first direction that is conductively connected to the top-to-bottom via-connector.

Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Abstract: An integrated circuit (IC) device includes first to fourth circuits configured to perform corresponding functions. The first to fourth circuits correspondingly include first to fourth active regions extending along a first direction, and further include a plurality of gate regions extending along a second direction transverse to the first direction. Adjacent gate regions among the plurality of gate regions are spaced from each other along the first direction by one gate region pitch. The first active region and the second active region correspondingly have a first source/drain region and a second source/drain region spaced from each other, along the first direction, by one gate region pitch. The first source/drain region is a drain region. The plurality of gate regions includes a dummy gate region between the first source/drain region and the second source/drain region. The third active region and the fourth active region share a common source region.

Abstract: An integrated circuit includes a first and second conductor, and a first and second pair of transistors. The first conductor is on a back-side of a substrate, extending in a first direction, and being configured to supply a first supply voltage. The second conductor is on the back-side of the substrate, and extending in the first direction. The first pair of transistors includes a first gate extending in a second direction, overlapping at least the second conductor, being located on a first level of a front-side of the substrate opposite from the back-side. The second pair of transistors includes a second gate extending in the second direction, overlapping at least the second conductor, being on the first level, and being separated from the first gate in the first direction. The second conductor electrically couples the first gate and the second gate together.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device comprises a first electrical conductor, a first additional electrical conductor, a first active region, a second electrical conductor, a second additional electrical conductor, and a second active region. The first electrical conductor has a first width and extends along a first direction. The first additional electrical conductor has a second width and extends along the first direction. The second width is greater than the first width. The first active region extends along a second direction perpendicular to the first direction. The first active region overlaps the first electrical conductor and the first additional electrical conductor from a top view perspective. The second electrical conductor has the first width and extends along the first direction. The second additional electrical conductor has the second width and extends along the first direction.

Abstract: An integrated circuit device includes a first-type active-region semiconductor structure extending and a second-type active-region semiconductor structure both extending in a first direction. The second-type active-region semiconductor structure is stacked with the first-type active-region semiconductor structure. The integrated circuit device also includes a front-side conductive layer above the two active-region semiconductor structures and a back-side conductive layer below the two active-region semiconductor structures. The integrated circuit device still includes a front-side power rail extending in the second direction in the front-side conductive layer and a back-side power rail extending in the second direction in the back-side conductive layer. The integrated circuit device further includes a first source conductive segment connected to the front-side power rail and a second source conductive segment connected to the back-side power rail.

Abstract: A non-transitory computer-readable medium contains thereon a cell library. The cell library includes a plurality of cells configured to be placed in a layout diagram of an integrated circuit (IC). Each cell among the plurality of cells includes a first active region inside a boundary of the cell. The first active region extends along a first direction. At least one gate region is inside the boundary. The at least one gate region extends across the first active region along a second direction transverse to the first direction. A first conductive region overlaps the first active region and a first edge of the boundary. The first conductive region is configured to form an electrical connection to the first active region. The plurality of cells includes at least one cell a width of which in the first direction is equal to one gate region pitch between adjacent gate regions of the IC.

Abstract: A method of making a semiconductor device includes manufacturing a first bridge pillar; manufacturing a first transistor channel bar and first transistor source/drain electrode, the first transistor S/D electrode electrically connecting to the first bridge pillar; manufacturing a second transistor channel bar and second transistor S/D electrode; manufacturing a first metal electrode, the first bridge pillar connecting the first transistor S/D electrode and first metal electrode; manufacturing a first via connected to the first metal electrode; and manufacturing a first conductive line connected to the first via. The first transistor S/D electrode and the second transistor S/D electrode are spaced apart by a first height, the first metal electrode is separate from the second transistor S/D electrode, the first bridge pillar is separate from the second transistor S/D electrode, and the first bridge pillar has a height in the first direction substantially equal to the first height.

Abstract: A semiconductor device includes a substrate, a gate structure, source/drain structures, a backside via, and a power rail. The gate structure extends along a first direction parallel with a front-side surface of the substrate. The backside via extends along a second direction parallel with the front-side surface of the substrate but perpendicular to the first direction, the backside via has a first portion aligned with one of the source/drain structures along the first direction and a second portion aligned with the gate structure along the first direction, the first portion of the backside via has a first width along the first direction, and the second portion of the backside via has a second width along the first direction, in which the first width is greater than the second width. The power rail is on a backside surface of the substrate and in contact with the backside via.