Abstract: A transistor structure and a formation method thereof are provided. The transistor structure includes a transistor device, formed on an active region of a semiconductor substrate, and including: a gate structure, disposed on the active region; gate spacers, formed along opposite sidewalls of the gate structure; source/drain structures, formed in recesses of the active region at opposite sides of the gate structure; and buried isolation structures, separately extending along bottom sides of the source/drain structures. Further, a channel portion of the active region between the source/drain structures is strained as a result of a strained etching stop layer lying above or dislocation stressors formed in the source/drain structures.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes an access transistor defined within an active region of a semiconductor substrate and a storage capacitor disposed on the access transistor. A recessed gate structure of the access transistor extends into the active region from above the active region. Source/drain contacts of the access transistor are disposed on the active region at opposite sides of the recessed gate structure. The storage capacitor includes: a composite bottom electrode, formed by alternately stacked first conductive layers and second conductive layers, wherein each second conductive layer is sandwiched between a pair of the first conductive layers, and tunnels laterally extend through the second conductive layers, respectively; a capacitor dielectric layer, covering inner and outer surfaces of the composite bottom electrode; and a top electrode, in contact with the composite bottom electrode through the capacitor dielectric layer.

Abstract: A C9orf72 DNA repeat expansion can be detected using a CRISPR Arrayed Repeat Detection System (CARDS). Based upon the compositions and methods supporting this platform primary cell cultures and/or blood cell smears can be tested under conventional clinical diagnostic laboratory conditions to diagnose genetically-based diseases having DNA repeat expansions, including but not limited to ALS. dCas9 constructs are also contemplated as having fluorescent proteins bound to any or all stem loop sequences, wherein detection of a plurality of dCas9 constructs having different colored fluorescent proteins can simultaneously detect at least six (6) different gene target loci.

Abstract: A C9orf72 DNA repeat expansion can be detected using a CRISPR Arrayed Repeat Detection System (CARDS). Based upon the compositions and methods supporting this platform primary cell cultures and/or blood cell smears can be tested under conventional clinical diagnostic laboratory conditions to diagnose genetically-based diseases having DNA repeat expansions, including but not limited to ALS. dCas9 constructs are also contemplated as having fluorescent proteins bound to any or all stem loop sequences, wherein detection of a plurality of dCas9 constructs having different colored fluorescent proteins can simultaneously detect at least six (6) different gene target loci.

Abstract: A C9orf72 DNA repeat expansion can be detected using a CRISPR Arrayed Repeat Detection System (CARDS). Based upon the compositions and methods supporting this platform primary cell cultures and/or blood cell smears can be tested under conventional clinical diagnostic laboratory conditions to diagnose genetically-based diseases having DNA repeat expansions, including but not limited to ALS. dCas9 constructs are also contemplated as having fluorescent proteins bound to any or all stem loop sequences, wherein detection of a plurality of dCas9 constructs having different colored fluorescent proteins can simultaneously detect at least six (6) different gene target loci.

Abstract: A wireless communication device including an integrated processing circuit, a first memory and a testing circuit is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit. The testing circuit is coupled to the first memory, and is capable of testing the first memory for determining if the first memory is an effective memory. The RF unit is put in a first package, the first memory is put in a second package, and the first package and the second package are packaged in a single device.

Abstract: A wireless communication device including an integrated processing circuit, a first memory and a testing circuit is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit. The testing circuit is coupled to the first memory, and is capable of testing the first memory for determining if the first memory is an effective memory. The RF unit and the first memory are placed in a single module.

Abstract: A low-power memory access method and associated apparatus are provided. The apparatus includes a memory controller and a processing unit. The memory controller is coupled to a first memory and a second memory, and includes: a memory management circuit, for allocating physical memory addresses of the first memory and the second memory and controlling access of the first memory and the second memory; and a direct-memory-access (DMA) controller. The processing unit is for accessing the first memory and the second memory via the memory controller. When the apparatus is in an active mode, the memory management circuit copies a portion of data stored in the second memory to the first memory for use by the processing unit, and records dirty data information when the portion of data in the first memory differs from that in the second memory.

Abstract: A media peripheral interface for communication between a processor and a peripheral device includes a clock port, a plurality of data I/Os, and a data strobe port. The clock port is operative to transfer a clock signal to the peripheral device. The data I/Os are provided for command transfer to the peripheral device and for data transfer to and from the peripheral device. The data strobe port is operative to transfer a data strobe signal to or from the peripheral device according to an instruction that the processor issues to the peripheral device. According to the clock signal, command information transferred via the data I/Os is captured. According to rising edges and falling edges of the data strobe signal, data transferred via the data I/Os are captured.

Abstract: A low-power wearable controller and associated control method are provided. The wearable controller includes: a processing unit; a memory unit; a peripheral interface unit including a plurality of peripheral interfaces; and a control module, coupled to the processing unit, the memory unit and the peripheral interface unit, wherein the control module is enabled when the wearable controller is operated in a first operation mode, and the control module is disabled when the wearable controller is operated in a second operation mode.

Abstract: A wireless communication device including an integrated processing circuit, a first memory and a testing circuit is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit. The testing circuit is coupled to the first memory, and is capable of testing the first memory for determining if the first memory is an effective memory. The RF unit is put in a first package, the first memory is put in a second package, and the first package and the second package are packaged in a single device.

Abstract: A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the integrated processing circuit and the first memory are packaged in a single semiconductor package.

Abstract: A storage apparatus, which is configured to receive an enter instruction to enter a deep sleep mode and configured to receive an awaking instruction to exit the deep sleep mode and to enter a normal mode. The storage apparatus keeps data stored therein in the deep sleep mode, and the storage apparatus can be normally accessed in the normal mode. If the storage apparatus is controlled to enter the normal mode while in the deep sleep mode, the storage apparatus enters the normal mode after the storage apparatus exits the deep sleep mode for a recovery time interval.

Abstract: A wireless communication device including an integrated processing circuit, a first memory and a testing circuit is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit. The testing circuit is coupled to the first memory, and is capable of testing the first memory for determining if the first memory is an effective memory. The RF unit and the first memory are placed in a single module.

Abstract: Examples of a dual-system architecture capable of fast switching between the operating systems are provided. A first operating system may perform one or more operations associated with an apparatus as an active operating system of the apparatus. The active operating system may be switched from the first operating system to a second operating system for the second operating system to perform a task responsive to a determination that the second operating system is required to perform the task.

Abstract: A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one or more of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the RF unit and the first memory are packaged in a single semiconductor device.

Abstract: A low-power wearable controller and associated control method are provided. The wearable controller includes: a processing unit; a memory unit; a peripheral interface unit including a plurality of peripheral interfaces; and a control module, coupled to the processing unit, the memory unit and the peripheral interface unit, wherein the control module is enabled when the wearable controller is operated in a first operation mode, and the control module is disabled when the wearable controller is operated in a second operation mode.

Abstract: A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one or more of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the RF unit and the first memory are packaged in a single semiconductor device.

Abstract: A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the integrated processing circuit and the first memory are packaged in a single semiconductor package.

Abstract: A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the integrated processing circuit and the first memory are packaged in a single semiconductor package.