Abstract: A virtual machine backup method, performed by a first host, includes: capturing a request to write data from a virtual machine to a hard disk image file, wherein the request includes written data and input and output location information, copying the written data to a temporary storage area, calculating a first key of the written data, storing the first key, the input and output location information into a first resource location structure, pausing an operation of the virtual machine and generating a second resource location structure according to the first resource location structure, the first key and a second key, and outputting a backup data set to a second host according to the second resource location structure, wherein the backup data set includes the second resource location structure and only one of existing data and the written data when the first key and the second key are the same.

Abstract: A data padding method includes outputting a second data matrix according to a first data matrix and a padding data. A second number of columns or a second number of rows of the second data matrix is proportional to a first number of columns or a first number of rows of the first data matrix.

Abstract: A data padding method includes adding at least one padding column or at least one padding row to a data matrix. One of a plurality of elements of the at least one padding row or the at least one padding column is different from another of the plurality of elements.

Abstract: A power supply system for CPU is disclosed. The CPU includes a plurality of dynamic voltage identification (VID) pins, and the power supply standard of the CPU conforms to a first standard. The power supply system includes a dynamic VID signal line set and a core voltage controller. The VID signal line set is coupled to the VID pins of the CPU. The core voltage controller conforms to a second standard and is coupled to a partial line set of the dynamic VID signal line set. The core voltage controller determines a core voltage to be output to the CPU according to the partial line set to conform to the first standard.

Abstract: A power supply system for CPU is disclosed. The CPU includes a plurality of dynamic voltage identification (VID) pins, and the power supply standard of the CPU conforms to a first standard. The power supply system includes a dynamic VID signal line set and a core voltage controller. The VID signal line set is coupled to the VID pins of the CPU. The core voltage controller conforms to a second standard and is coupled to a partial line set of the dynamic VID signal line set. The core voltage controller determines a core voltage to be output to the CPU according to the partial line set to conform to the first standard.

Abstract: A power supply system for CPU is disclosed. The CPU includes a plurality of dynamic voltage identification (VID) pins, and the power supply standard of the CPU conforms to a first standard. The power supply system includes a VID signal line set and a core voltage controller. The VID signal line set is coupled to the VID pins of the CPU, wherein the VID signal line set includes a least significant bit (LSB) signal line set and a most significant bit (MSB) signal line set. The core voltage controller conforms to a second standard and is coupled to the MSB signal line set to determine the core voltage to be output to the CPU according to the bit state of each MSB signal line in the MSB signal line set, so that the power supply system can conform to the first standard.

Abstract: A power control system includes a voltage control circuit and a plurality of balance circuits. The voltage control circuit controls a voltage level at an output of the power control system according to a reference voltage. Each of the plurality of balancing circuits outputs a current, whose magnitude is a specific ratio to an output current outputted from the voltage control circuit. The power control system is capable of balancing output currents of the voltage control circuit and the plurality of balance circuits in order to share output load of the power control system.

Abstract: A power supply system for CPU is disclosed. The CPU includes a plurality of dynamic voltage identification (VID) pins, and the power supply standard of the CPU conforms to a first standard. The power supply system includes a VID signal line set and a core voltage controller. The VID signal line set is coupled to the VID pins of the CPU, wherein the VID signal line set includes a least significant bit (LSB) signal line set and a most significant bit (MSB) signal line set. The core voltage controller conforms to a second standard and is coupled to the MSB signal line set to determine the core voltage to be output to the CPU according to the bit state of each MSB signal line in the MSB signal line set, so that the power supply system can conform to the first standard.

Abstract: A power control system includes a voltage control circuit and a plurality of balance circuits. The voltage control circuit controls a voltage level at an output of the power control system according to a reference voltage. Each of the plurality of balancing circuits outputs a current, whose magnitude is a specific ratio to an output current outputted from the voltage control circuit. The power control system is capable of balancing output currents of the voltage control circuit and the plurality of balance circuits in order to share output load of the power control system.

Abstract: A clamp for quickly, effectively and safely removing a cathode collar from an HDP deposition chamber for routine maintenance, cleaning or replacement of the collar. The clamp includes a pair of clamp plates which are capable of pivoting movement on respective ends of a connecting rod. A clamp shoe for gripping a corresponding edge of the annular collar is provided on the bottom end of each clamp plate, and a turnbuckle is fitted with a pair of threaded shafts which engage the upper end portions of the respective clamp plates. By rotating the turnbuckle, the threaded shafts are advanced away from each other against the clamp plates, which pivot on the connecting rod and cause the clamp shoes to tightly engage respective edges of the collar. The clamp is grasped to lift the collar from the chamber and replace the collar in the chamber after cleaning or maintenance.

Abstract: A clamp for quickly, effectively and safely removing a cathode collar from an HDP deposition chamber for routine maintenance, cleaning or replacement of the collar. The clamp includes a pair of clamp plates which are capable of pivoting movement on respective ends of a connecting rod. A clamp shoe for gripping a corresponding edge of the annular collar is provided on the bottom end of each clamp plate, and a turnbuckle is fitted with a pair of threaded shafts which engage the upper end portions of the respective clamp plates. By rotating the turnbuckle, the threaded shafts are advanced away from each other against the clamp plates, which pivot on the connecting rod and cause the clamp shoes to tightly engage respective edges of the collar. The clamp is grasped to lift the collar from the chamber and replace the collar in the chamber after cleaning or maintenance.

Abstract: A method and system for comparing design block views comprising receiving a first design block view, receiving a second design block view, and comparing the first design block view with the second design block view to determine whether the first design block view is logically equivalent to the second design block view, the second design block view contains data representing self-timed circuits or a memory array.

Abstract: The system provided attaches a cartridge-type central processor unit (CPU) to a motherboard and includes a first device, a second device and a third device. The first device has a slot for receiving the cartridge-type CPU. The second device is disposed below the motherboard to fortify the strength of the motherboard. The third device functions to attach the first device and the motherboard to the second device. The weight of the cartridge-type CPU, via the first device and the third device, is substantially transferred to the second device with the second device being a primary carrier of weight of the cartridge-type CPU. Since weight of the cartridge-type CPU is not carried by the motherboard, motherboard will experience no damage.