Abstract: A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.

Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device includes forming nanowire structures stacked over a substrate and spaced apart from one another, and forming a dielectric material surrounding the nanowire structures. The dielectric material has a first nitrogen concentration. The method also includes treating the dielectric material to form a treated portion. The treated portion of the dielectric material has a second nitrogen concentration that is greater than the first nitrogen concentration. The method also includes removing the treating portion of the dielectric material, thereby remaining an untreated portion of the dielectric material as inner spacer layers; and forming the gate stack surrounding nanowire structures and between the inner spacer layers.

Abstract: A method includes forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked over a substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure uncovered by the dummy gate structure; performing a selective etching process to laterally recess the first semiconductor layers, including injecting a hydrogen-containing gas from a first gas source of a processing tool to the first semiconductor layers and the second semiconductor layers; and injecting an F2 gas from a second gas source of the processing tool to the first semiconductor layers and the second semiconductor layers; forming inner spacers on opposite end surfaces of the laterally recessed first semiconductor layers of the fin structure; and replacing the dummy gate structure and the first semiconductor layers with a metal gate structure.

Abstract: Methods, devices, computer readable media and apparatus are presented for providing configurable task management, such as data collection management, on a wireless device. Task management provides conditions and associated actions which may be dynamically configured and implemented in conjunction with any application executed on the wireless device.

Abstract: Methods, devices, computer readable media and apparatus are presented for providing configurable task management, such as data collection management, on a wireless device. Task management provides conditions and associated actions which may be dynamically configured and implemented in conjunction with any application executed on the wireless device.

Abstract: Multi-phase, single layer, non-interdiffusing M-Mo back contact metallized films, where M is selected from Cu, Ga, or mixtures thereof, for CIS cells are deposited by a sputtering process on suitable substrates, preferably glass or alumina, to prevent delamination of the CIS from the back contact layer. Typical CIS compositions include CuXSe.sub.2 where X is In or/and Ga. The multi-phase mixture is deposited on the substrate in a manner to provide a columnar microstructure, with micro-vein Cu or/and Ga regions which partially or fully vertically penetrate the entire back contact layer. The CIS semiconductor layer is then deposited by hybrid sputtering and evaporation process. The Cu/Ga-Mo deposition is controlled to produce the single layer two-phase columnar morphology with controllable Cu or Ga vein size less than about 0.01 microns in width.