Abstract: A device includes a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer. The second dielectric layer and the first dielectric layer have different material compositions. A metal-insulator-metal (MIM) structure is embedded in the second dielectric layer. A third dielectric layer is disposed over the second dielectric layer. The third dielectric layer and the second dielectric layer have different material compositions. The first dielectric layer or the third dielectric layer may contain silicon nitride (SiN), the second dielectric layer may contain silicon oxide (SiO2).

Abstract: A method and semiconductor device including a substrate having one or more semiconductor devices. In some embodiments, the device further includes a first passivation layer disposed over the one or more semiconductor devices, and a metal-insulator-metal (MIM) capacitor structure formed over the first passivation layer. In some embodiments, the MIM capacitor structure includes a first conductor plate layer, an insulator layer on the first conductor plate layer, and a second conductor plate layer on the insulator layer. In some examples, the insulator layer includes a metal oxide sandwich structure.

Abstract: An interconnect structure on a semiconductor die includes: a lower conductive layer; an upper conductive layer disposed above the lower conductive layer; and a VIA disposed between the lower conductive layer and the upper conductive layer. The VIA includes: a primary interconnect structure and a sacrificial stress barrier ring disposed around the primary interconnect structure and separated a distance from the primary interconnect structure. A fabrication method for the interconnect structure includes: forming a dielectric layer over a lower conductive layer; patterning photoresist (PR) layer over the dielectric layer to define a location for a plurality of VIA trenches, wherein the patterning includes patterning the PR layer to provide a center opening for the VIA trenches that is surrounded by a ring opening for the VIA trenches, wherein the center opening and the ring opening are spaced apart.

Abstract: Semiconductor structures and methods are provided. An exemplary method includes depositing a first conductive material layer over a substrate, patterning the first conductive material layer to form a first conductor plate over the substrate, forming a first high-K dielectric layer over the first conductor plate, forming a second high-K dielectric layer on the first high-K dielectric layer, forming a third high-K dielectric layer on the second high-K dielectric layer, and forming a second conductor plate over the third high-K dielectric layer and vertically overlapped with the first conductor plate, where a composition of the first high-K dielectric layer is the same as a composition of the third high-K dielectric layer and is different from a composition of the second high-K dielectric layer.